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Author SHA1 Message Date
tehpola
5c67851bd0 GEN_STFS and GEN_STFD. 2009-10-09 02:10:09 +00:00
tehpola
a5295696ef Put rdram and reg_cop1_fgr_64 in registers, begin support for FPR 
mapping.
 2009-10-09 02:09:51 +00:00
tehpola
94857e836f Updated Makefiles and removed warning from Register-Cache.c 2009-10-09 02:09:14 +00:00
tehpola
78e7a76d7e Moved register mapping code into its own file. 2009-10-09 02:08:00 +00:00
tehpola
a01e2c4a01 More Interpreted stuff undefined due to successful recompilation :) 2009-10-09 02:07:34 +00:00
tehpola
742050ff02 Fixed bug in DSRAV when (rs) < 32 and MSb of (rt) is 1. 2009-10-09 02:06:58 +00:00
tehpola
5adef44c7d Fixing typos. 2009-10-09 02:06:11 +00:00
tehpola
9481f6ac1d Added GEN_SUBFIC. 2009-10-09 02:05:19 +00:00
tehpola
f4e6144554 Masking shift amount in DSLLV, DSRLV, and DSRAV. 2009-10-09 02:04:59 +00:00
tehpola
dd24b1d88c Implementation (untested) of DSLLV, DSRLV, and DSRAV. 2009-10-09 02:04:39 +00:00
tehpola
871a8fe2a1 Fixed SLTI and SLTIU. 2009-10-09 02:04:15 +00:00
tehpola
2585ed7417 Latest #defines for Interpreter.h with all working functions. 2009-10-09 02:03:57 +00:00
tehpola
51d58a794a Oops, I wasn't mapping source registers on MULTU, DIV, or DIVU. 2009-10-09 02:03:41 +00:00
tehpola
d38d89ba86 Implementation (untested) of DSLL32, DSRL32, DSRA32. 2009-10-09 02:03:24 +00:00
tehpola
2a1867e1c4 Update to Interpreter.h, removes duplicate defines for things like DADD and DADDU. Also interpreting as little as can be (for now). 2009-10-09 02:03:08 +00:00
tehpola
c9ca92ed84 Implementations (untested) of DSLL, DSRL, DSRA. 2009-10-09 02:02:35 +00:00
tehpola
e4ab90d15e Addition of 64-bit instructions. 2009-10-09 02:02:20 +00:00
tehpola
e2e8857dbc Fixed up condional compilation for double-word instructions to check both INTERPRET_DW or the appropriate flag for that instruction. Implementations 
for DADDI, DADD, DSUB, but not set to compile those yet.
 2009-10-09 02:02:04 +00:00
emukidid
3af4cad439 Updated ROM-Cache.c to work properly as it does in the main trunk. Purely so I can test more on GC. 2009-10-08 23:28:11 +00:00
tehpola
7011e21959 Commenting out INTERPRET_HILO. 2009-10-08 15:55:51 +00:00
tehpola
bf8f2bdbc8 Reworked register mappings which now support 64-bit mappings. Properly defined mflo,mfhi,mtlo,mthi to work correctly (64-bit), but INTERPRET_HILO is 
still defined.
 2009-10-08 15:55:12 +00:00
tehpola
ba28106447 Recompiling SLT* instructions now. It looks like SLTIU was the offender as the immediate wasn't sign extended and the operands to the subfc were 
backwards.
 2009-10-08 15:53:05 +00:00
tehpola
2f42a4e5c7 Whoops, on the last revision, I loaded the destination addresss rather than the next instruction's address. 2009-10-08 15:52:11 +00:00
tehpola
032a848d20 Make sure branches out which aren't taken still call gen_interupt if necessary (untested). 2009-10-08 15:49:30 +00:00
tehpola
ca0bd81311 Set delaySlotNext for first instruction in block when the previous instruction was a jump/branch. Added JR/JALR to mips_is_jump. 2009-10-08 15:46:47 +00:00
tehpola
c34b876ce5 Use the jump_pad to the trampoline on likely branches which need to take an interrupt. 2009-10-08 15:46:00 +00:00
tehpola
1c93c2de60 Fixed issue where I would jump over a delay slot which wasn't there because it was in the next block and thus causing bad behavior. 2009-10-08 15:42:50 +00:00
tehpola
3bf29557e1 Avoid any nasty dangling pointer mistakes in RecompCache_release. 2009-10-08 15:40:32 +00:00
tehpola
2d9e0fe69f RecompCache fix (I wasn't allocating again after a block was released). 2009-10-08 15:39:39 +00:00
emukidid
d0b0623a3a Conditional branches now use B instead of BC to traverse the block (because it is too large). 2009-10-08 13:25:51 +00:00
emukidid
50763e6e1d Fixed the off-by-one wrt to branches to the first instruction in the next block (or was it the last in the previous?). 2009-10-08 13:24:29 +00:00
emukidid
01104315de Don't write past the end of code_addr when recompiling a delay slot that belongs in the next block. 2009-10-08 13:21:42 +00:00
emukidid
a8871208aa Clearing up recompilation delay slot flags (just more obvious names) and fixing a small typo which would cause the last revision to not compile. 2009-10-08 13:20:56 +00:00
emukidid
89c8edd59e A few small misc fixes from ps3. 2009-10-08 13:20:04 +00:00
emukidid
0cedc64de0 Fix code_addr for instructions which flush previous registers' mappings. 2009-10-08 13:19:15 +00:00
emukidid
6d02bddc7d Flush delay slots of interpreted branches so their register mappings don't leak into the next basic block. 2009-10-08 13:18:19 +00:00
emukidid
8209e94237 Set noCheckInterrupt in decodeNInterpret if the dynarec needs to bounce back to the trampoline because the PC was changed. 2009-10-08 13:17:28 +00:00
emukidid
db015157ee Fixes behavior wrt Count when continuing execution between adjacent blocks (without branching) by setting a flag. 
Fixes JALR's incorrect linking address.
 2009-10-08 13:16:40 +00:00
emukidid
69818ad096 Conditional linking branches fix. 2009-10-08 13:15:27 +00:00
emukidid
0f70f115b6 SRLV fix. 2009-10-08 13:14:25 +00:00
emukidid
392fa0dbc7 Conditional linking branches fix. 2009-10-08 13:13:00 +00:00
emukidid
22eb3962ac Likely delay slot update_count fix. 2009-10-08 13:11:59 +00:00
emukidid
9ec0b4fa3c emukidid directory now has all the latest IRC channel fixes as well as: 4mb fix and printing gen_interrupt stuff to the desktop. Also disabled the printing in wrappers.c 2009-10-07 13:17:16 +00:00
emukidid
1c9cadc1f5 Created emukidid branch from tehpola r468 branch 2009-10-07 12:48:48 +00:00
emukidid
66f4039cc1 Edited wiki page through web user interface. 2009-09-30 11:29:10 +00:00
emukidid
76e36c4c25 Edited wiki page through web user interface. 2009-09-30 11:01:33 +00:00
emukidid
37046f81cb Deleting wiki page CompatibilityList. 2009-09-30 08:40:39 +00:00
emukidid
2728cffbd4 Edited wiki page through web user interface. 2009-03-20 23:39:54 +00:00
tehpola
cc3c249cff Consilidated memory LUTs into one memory LUT which points to smaller 
LUTs for read/write byte/hword/word/double.  Saved substantial amount of 
memory.
 2009-02-23 18:47:42 +00:00
sepp256
9cfe68e17d PS mtx and vector transforms added to glN64, complements of tehpola. 2009-02-08 20:29:13 +00:00