tehpola
|
bd42eaeebe
|
Added invalidateRegister and invalidateFPR and (untested) implementation
of MTC1 and DMTC1.
|
2009-10-09 02:15:14 +00:00 |
|
tehpola
|
801c0ef756
|
Recompile CVT.D.S and CVT.S.D.
|
2009-10-09 02:14:33 +00:00 |
|
tehpola
|
359abcdac0
|
Correcting GEN_FMUL to use RC for the second operand rather than RB.
|
2009-10-09 02:14:13 +00:00 |
|
tehpola
|
3c454def0a
|
FPR mapping seems to work by indirectly using reg_cop1_simple and
reg_cop1_double rather than the array directly now. Not all recompiled
FP instructions work correctly though.
|
2009-10-09 02:13:38 +00:00 |
|
tehpola
|
5c5c0f01e3
|
Fixed a couple minor FPR mapping bugs.
|
2009-10-09 02:13:11 +00:00 |
|
tehpola
|
20256d7c09
|
Added FP recompilation code, but none of the instructions work yet.
|
2009-10-09 02:12:40 +00:00 |
|
tehpola
|
f32e6e125d
|
Finishing up FPR mapping code.
|
2009-10-09 02:12:13 +00:00 |
|
tehpola
|
7e41531a61
|
Removed old TODO regarding 64-bit mappings.
|
2009-10-09 02:11:37 +00:00 |
|
tehpola
|
8d36bfea83
|
Recompilation of SW/SH/SB, removed gen_interrupt prints from screen (it would slow things down).
|
2009-10-09 02:11:18 +00:00 |
|
tehpola
|
dd836b8ee3
|
LW now detects whether the address is in SP_DMEM or rdram and loads from
the correct location.
|
2009-10-09 02:10:53 +00:00 |
|
tehpola
|
c6e2894ab5
|
LB,SB,LH,SH,LW,SW added to MIPS-to-PPC.c but still interpreted via Interpreter.h
|
2009-10-09 02:10:27 +00:00 |
|
tehpola
|
5c67851bd0
|
GEN_STFS and GEN_STFD.
|
2009-10-09 02:10:09 +00:00 |
|
tehpola
|
a5295696ef
|
Put rdram and reg_cop1_fgr_64 in registers, begin support for FPR
mapping.
|
2009-10-09 02:09:51 +00:00 |
|
tehpola
|
94857e836f
|
Updated Makefiles and removed warning from Register-Cache.c
|
2009-10-09 02:09:14 +00:00 |
|
tehpola
|
78e7a76d7e
|
Moved register mapping code into its own file.
|
2009-10-09 02:08:00 +00:00 |
|
tehpola
|
a01e2c4a01
|
More Interpreted stuff undefined due to successful recompilation :)
|
2009-10-09 02:07:34 +00:00 |
|
tehpola
|
742050ff02
|
Fixed bug in DSRAV when (rs) < 32 and MSb of (rt) is 1.
|
2009-10-09 02:06:58 +00:00 |
|
tehpola
|
5adef44c7d
|
Fixing typos.
|
2009-10-09 02:06:11 +00:00 |
|
tehpola
|
9481f6ac1d
|
Added GEN_SUBFIC.
|
2009-10-09 02:05:19 +00:00 |
|
tehpola
|
f4e6144554
|
Masking shift amount in DSLLV, DSRLV, and DSRAV.
|
2009-10-09 02:04:59 +00:00 |
|
tehpola
|
dd24b1d88c
|
Implementation (untested) of DSLLV, DSRLV, and DSRAV.
|
2009-10-09 02:04:39 +00:00 |
|
tehpola
|
871a8fe2a1
|
Fixed SLTI and SLTIU.
|
2009-10-09 02:04:15 +00:00 |
|
tehpola
|
2585ed7417
|
Latest #defines for Interpreter.h with all working functions.
|
2009-10-09 02:03:57 +00:00 |
|
tehpola
|
51d58a794a
|
Oops, I wasn't mapping source registers on MULTU, DIV, or DIVU.
|
2009-10-09 02:03:41 +00:00 |
|
tehpola
|
d38d89ba86
|
Implementation (untested) of DSLL32, DSRL32, DSRA32.
|
2009-10-09 02:03:24 +00:00 |
|
tehpola
|
2a1867e1c4
|
Update to Interpreter.h, removes duplicate defines for things like DADD and DADDU. Also interpreting as little as can be (for now).
|
2009-10-09 02:03:08 +00:00 |
|
tehpola
|
c9ca92ed84
|
Implementations (untested) of DSLL, DSRL, DSRA.
|
2009-10-09 02:02:35 +00:00 |
|
tehpola
|
e4ab90d15e
|
Addition of 64-bit instructions.
|
2009-10-09 02:02:20 +00:00 |
|
tehpola
|
e2e8857dbc
|
Fixed up condional compilation for double-word instructions to check both INTERPRET_DW or the appropriate flag for that instruction. Implementations
for DADDI, DADD, DSUB, but not set to compile those yet.
|
2009-10-09 02:02:04 +00:00 |
|
emukidid
|
3af4cad439
|
Updated ROM-Cache.c to work properly as it does in the main trunk. Purely so I can test more on GC.
|
2009-10-08 23:28:11 +00:00 |
|
tehpola
|
7011e21959
|
Commenting out INTERPRET_HILO.
|
2009-10-08 15:55:51 +00:00 |
|
tehpola
|
bf8f2bdbc8
|
Reworked register mappings which now support 64-bit mappings. Properly defined mflo,mfhi,mtlo,mthi to work correctly (64-bit), but INTERPRET_HILO is
still defined.
|
2009-10-08 15:55:12 +00:00 |
|
tehpola
|
ba28106447
|
Recompiling SLT* instructions now. It looks like SLTIU was the offender as the immediate wasn't sign extended and the operands to the subfc were
backwards.
|
2009-10-08 15:53:05 +00:00 |
|
tehpola
|
2f42a4e5c7
|
Whoops, on the last revision, I loaded the destination addresss rather than the next instruction's address.
|
2009-10-08 15:52:11 +00:00 |
|
tehpola
|
032a848d20
|
Make sure branches out which aren't taken still call gen_interupt if necessary (untested).
|
2009-10-08 15:49:30 +00:00 |
|
tehpola
|
ca0bd81311
|
Set delaySlotNext for first instruction in block when the previous instruction was a jump/branch. Added JR/JALR to mips_is_jump.
|
2009-10-08 15:46:47 +00:00 |
|
tehpola
|
c34b876ce5
|
Use the jump_pad to the trampoline on likely branches which need to take an interrupt.
|
2009-10-08 15:46:00 +00:00 |
|
tehpola
|
1c93c2de60
|
Fixed issue where I would jump over a delay slot which wasn't there because it was in the next block and thus causing bad behavior.
|
2009-10-08 15:42:50 +00:00 |
|
tehpola
|
3bf29557e1
|
Avoid any nasty dangling pointer mistakes in RecompCache_release.
|
2009-10-08 15:40:32 +00:00 |
|
tehpola
|
2d9e0fe69f
|
RecompCache fix (I wasn't allocating again after a block was released).
|
2009-10-08 15:39:39 +00:00 |
|
emukidid
|
d0b0623a3a
|
Conditional branches now use B instead of BC to traverse the block (because it is too large).
|
2009-10-08 13:25:51 +00:00 |
|
emukidid
|
50763e6e1d
|
Fixed the off-by-one wrt to branches to the first instruction in the next block (or was it the last in the previous?).
|
2009-10-08 13:24:29 +00:00 |
|
emukidid
|
01104315de
|
Don't write past the end of code_addr when recompiling a delay slot that belongs in the next block.
|
2009-10-08 13:21:42 +00:00 |
|
emukidid
|
a8871208aa
|
Clearing up recompilation delay slot flags (just more obvious names) and fixing a small typo which would cause the last revision to not compile.
|
2009-10-08 13:20:56 +00:00 |
|
emukidid
|
89c8edd59e
|
A few small misc fixes from ps3.
|
2009-10-08 13:20:04 +00:00 |
|
emukidid
|
0cedc64de0
|
Fix code_addr for instructions which flush previous registers' mappings.
|
2009-10-08 13:19:15 +00:00 |
|
emukidid
|
6d02bddc7d
|
Flush delay slots of interpreted branches so their register mappings don't leak into the next basic block.
|
2009-10-08 13:18:19 +00:00 |
|
emukidid
|
8209e94237
|
Set noCheckInterrupt in decodeNInterpret if the dynarec needs to bounce back to the trampoline because the PC was changed.
|
2009-10-08 13:17:28 +00:00 |
|
emukidid
|
db015157ee
|
Fixes behavior wrt Count when continuing execution between adjacent blocks (without branching) by setting a flag.
Fixes JALR's incorrect linking address.
|
2009-10-08 13:16:40 +00:00 |
|
emukidid
|
69818ad096
|
Conditional linking branches fix.
|
2009-10-08 13:15:27 +00:00 |
|