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Merge latest core changes from upstream repo

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This commit is contained in:
rdanbrook 2021-12-11 10:15:29 -05:00
parent 58645c0da5
commit 9c9aaf7700
3 changed files with 78 additions and 8 deletions
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11
source/core/NstCpu.cpp
View file

@ -124,7 +124,7 @@ namespace Nes
0x00, 0x20, 0x00, 0x20, 0x04, 0x04, 0x04, 0x04,
0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08,
0x00, 0x20, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08,
0x00, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
0x00, 0x10, 0x00, 0x00, 0x10, 0x10, 0x10, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@ -2114,11 +2114,12 @@ namespace Nes
}
// Unofficial Opcodes SHX/SHY are edge cases
#define NES_I_W_U(instr_,addr_,hex_) \
#define NES_I_W_U(instr_,hex_) \
\
void Cpu::op##hex_() \
{ \
const uint dst = addr_##_W(); \
const uint dst = FetchPc16(); \
cycles.count += cycles.clock[3]; \
instr_(dst); \
}
@ -2379,8 +2380,8 @@ namespace Nes
NES_I_W_A( Sha, AbsY, 0x9F )
NES_I_W_A( Sha, IndY, 0x93 )
NES_I_W_A( Shs, AbsY, 0x9B )
NES_I_W_U( Shx, Abs, 0x9E ) // Edge case: AbsY done internally
NES_I_W_U( Shy, Abs, 0x9C ) // Edge case: AbsX done internally
NES_I_W_U( Shx, 0x9E ) // Edge case: AbsY done internally
NES_I_W_U( Shy, 0x9C ) // Edge case: AbsX done internally
NES_IRW__( Slo, Zpg, 0x07 )
NES_IRW__( Slo, ZpgX, 0x17 )
NES_IRW__( Slo, Abs, 0x0F )

68
source/core/NstPpu.cpp
View file

@ -735,6 +735,17 @@ namespace Nes
return (regs.ctrl[1] & Regs::CTRL1_EMPHASIS) << 1;
}
NST_FORCE_INLINE void Ppu::UpdateDecay(byte mask)
{
Cycle curCyc = cpu.GetCycles();
for (uint i = 0; i < 8; ++i)
{
if (mask & (1 << i))
decay.timestamp[i] = curCyc;
}
}
NES_POKE_D(Ppu,2000)
{
Update( cycles.one );
@ -747,6 +758,8 @@ namespace Nes
oam.height = (data >> 2 & 8) + 8;
io.latch = data;
UpdateDecay(0xFF);
data = regs.ctrl[0] ;
regs.ctrl[0] = io.latch;
@ -786,6 +799,8 @@ namespace Nes
}
io.latch = data;
UpdateDecay(0xFF);
data = (regs.ctrl[1] ^ data) & (Regs::CTRL1_EMPHASIS|Regs::CTRL1_MONOCHROME);
regs.ctrl[1] = io.latch;
@ -813,13 +828,22 @@ namespace Nes
{
Update( cycles.one, address );
byte mask = 0xE0;
uint status = regs.status & 0xFF;
regs.status &= (Regs::STATUS_VBLANK^0xFFU);
scroll.toggle = 0;
io.latch = (io.latch & Regs::STATUS_LATCH) | status;
UpdateDecay(mask);
return io.latch;
Cycle curCyc = cpu.GetCycles();
for (uint i = 0; i < 5; ++i)
{
if ((curCyc - decay.timestamp[i]) < 24576)
mask |= (1 << i);
}
return io.latch & mask;
}
NES_PEEK_A(Ppu,2002_RC2C05_01_04)
@ -843,6 +867,7 @@ namespace Nes
regs.oam = data;
io.latch = data;
UpdateDecay(0xFF);
}
NES_POKE_D(Ppu,2004)
@ -852,6 +877,9 @@ namespace Nes
NST_ASSERT( regs.oam < Oam::SIZE );
NST_VERIFY( IsDead() );
io.latch = data;
UpdateDecay(0xFF);
if (IsDead())
{
if ((regs.oam & 0x03) == 0x02)
@ -864,7 +892,6 @@ namespace Nes
byte* const NST_RESTRICT value = oam.ram + regs.oam;
regs.oam = (regs.oam + 1) & 0xFF;
io.latch = data;
*value = data;
}
@ -875,12 +902,14 @@ namespace Nes
if (!(regs.ctrl[1] & Regs::CTRL1_BG_SP_ENABLED) || cpu.GetCycles() - (cpu.GetFrameCycles() - (341 * 241) * cycles.one) >= (341 * 240) * cycles.one)
{
io.latch = oam.ram[regs.oam];
UpdateDecay(0xFF);
}
else
{
Update( cycles.one );
io.latch = oam.latch;
UpdateDecay(0xFF);
}
return io.latch;
@ -895,6 +924,7 @@ namespace Nes
if (cpu.GetCycles() >= cycles.reset)
{
io.latch = data;
UpdateDecay(0xFF);
if (scroll.toggle ^= 1)
{
@ -917,6 +947,7 @@ namespace Nes
if (cpu.GetCycles() >= cycles.reset)
{
io.latch = data;
UpdateDecay(0xFF);
if (scroll.toggle ^= 1)
{
@ -945,6 +976,7 @@ namespace Nes
return;
io.latch = data;
UpdateDecay(0xFF);
if ((address & 0x3F00) == 0x3F00)
{
@ -976,27 +1008,54 @@ namespace Nes
NES_PEEK_A(Ppu,2007)
{
byte mask = 0xFF;
byte cache = io.latch;
Update( cycles.one, address );
Cycle curCyc = cpu.GetCycles();
Cycle delta = curCyc - decay.rd2007;
decay.rd2007 = curCyc;
bool fastread = (delta <= 12);
address = scroll.address & 0x3FFF;
UpdateVramAddress();
if (!(regs.ctrl[1] & Regs::CTRL1_BG_SP_ENABLED) || (scanline == SCANLINE_VBLANK))
UpdateAddressLine(scroll.address & 0x3fff);
io.latch = (address & 0x3F00) != 0x3F00 ? io.buffer : palette.ram[address & 0x1F] & Coloring();
if ((address & 0x3F00) == 0x3F00) // Palette
{
io.latch = (io.latch & 0xC0) | palette.ram[address & 0x1F] & Coloring();
mask = 0x3F;
}
else // Non-Palette
{
io.latch = io.buffer;
}
UpdateDecay(mask);
io.buffer = (address >= 0x2000 ? nmt.FetchName( address ) : chr.FetchPattern( address ));
if (fastread)
io.latch = cache;
return io.latch;
}
NES_POKE_D(Ppu,2xxx)
{
io.latch = data;
UpdateDecay(0xFF);
}
NES_PEEK(Ppu,2xxx)
{
if ((cpu.GetCycles() - decay.timestamp[0]) > 24576)
return 0;
return io.latch;
}
@ -1035,10 +1094,13 @@ namespace Nes
}
io.latch = oamRam[0xFF];
UpdateDecay(0xFF);
}
else do
{
io.latch = cpu.Peek( data++ );
UpdateDecay(0xFF);
cpu.StealCycles( cpu.GetClock() );
Update( cycles.one );

7
source/core/NstPpu.hpp
View file

@ -186,6 +186,7 @@ namespace Nes
NST_FORCE_INLINE uint FetchSpPattern() const;
NST_FORCE_INLINE void FetchBgPattern0();
NST_FORCE_INLINE void FetchBgPattern1();
NST_FORCE_INLINE void UpdateDecay(byte);
NST_FORCE_INLINE void EvaluateSpritesEven();
NST_FORCE_INLINE void EvaluateSpritesOdd();
@ -407,6 +408,12 @@ namespace Nes
Cycle reset;
} cycles;
struct
{
Cycle timestamp[8];
Cycle rd2007;
} decay;
Io io;
Regs regs;
Scroll scroll;