Emulation/n64js
1
0
Fork 0
mirror of https://github.com/hulkholden/n64js.git synced 2025-04-02 10:51:54 -04:00
Code Issues Projects Releases Packages Wiki Activity

Commit graph

  • b230aa4d96 Dedupe executeVRCPH and executeVRSQH. Paul Holden 2023-08-13 23:58:39 +01:00
  • a77efb5fd2 Fix arg order for vectorSetAccFromReg. Paul Holden 2023-08-13 23:56:18 +01:00
  • ea1e9ac903 Reorder functions. Paul Holden 2023-08-13 23:54:51 +01:00
  • d87889e285 Add a vectorLogical helper. Paul Holden 2023-08-13 23:53:50 +01:00
  • 7bf199dc50 Init select in the loop initialiser. Paul Holden 2023-08-13 23:47:54 +01:00
  • ca77ffd62b Use vectorSetAccFromReg helper. Paul Holden 2023-08-13 23:46:59 +01:00
  • 262a68b013 Use setVecFromAccLow for VSUBC. Paul Holden 2023-08-13 23:46:23 +01:00
  • a56d52a962 Use setVecFromAccLow for VADDC. Paul Holden 2023-08-13 23:46:11 +01:00
  • 3a71c201c3 Update VMRG to use setVecFromAccLow. Paul Holden 2023-08-13 23:39:15 +01:00
  • 9e7bc6b3f3 Update logical ops to use setVecFromAccLow. Paul Holden 2023-08-13 23:38:37 +01:00
  • a760ab7b7a Set the register directly from the accumulator. Paul Holden 2023-08-13 23:26:54 +01:00
  • 3fdb04ddb4 Dedupe vectorSetAccFromReg. Paul Holden 2023-08-13 23:24:52 +01:00
  • 9d0c2e1e57 Add some helpers to reduce duplication across vector multiply instructions. Paul Holden 2023-08-13 23:08:40 +01:00
  • bac7ba9f9a Rename the main output result. Paul Holden 2023-08-13 22:25:24 +01:00
  • 92002d128d Add an accessor for setting the low accumulator bits. Paul Holden 2023-08-13 22:10:46 +01:00
  • 024fce1c80 Fix VCO shifting. Paul Holden 2023-08-13 21:51:25 +01:00
  • 6f28ab9ca3 Rename locals consistently. Paul Holden 2023-08-13 21:28:22 +01:00
  • 911b423571 Set the output directly from the accumulator regs in a separate pass. Paul Holden 2023-08-13 21:03:36 +01:00
  • af373c34bc Remove stray comment. Paul Holden 2023-08-13 17:03:05 +01:00
  • d294761c09 Inline accum48SignExtend. Paul Holden 2023-08-13 17:02:37 +01:00
  • ef6d13ca72 Add some accessors to simplfy vector multiply ops. Paul Holden 2023-08-13 17:01:23 +01:00
  • 7815e6193c Get rid of newAccum temporary. Paul Holden 2023-08-13 15:22:14 +01:00
  • 130eebf18a Remove TODOs: this seems to be working correctly. Paul Holden 2023-08-13 15:19:33 +01:00
  • b36a070308 Emulate accumulator overflow correctly. Paul Holden 2023-08-13 15:16:20 +01:00
  • f51236dee5 Implement VEXTT, VEXTQ, VEXTN, VINST, VINSQ, VINSN (all vectorZero). Paul Holden 2023-08-12 14:35:00 +01:00
  • 06ed51fbe5 Implement VNULL. Paul Holden 2023-08-12 14:26:10 +01:00
  • ff3ed61b52 Implement VCH. Paul Holden 2023-08-12 14:22:43 +01:00
  • 77437a5a9b Tidy VCL. Paul Holden 2023-08-12 13:05:46 +01:00
  • f5056821c2 Implement VCL. Paul Holden 2023-08-12 13:03:04 +01:00
  • d0b190b060 Add accessors for VCC hi and lo bits. Paul Holden 2023-08-12 09:26:05 +01:00
  • 6708988672 vuVCOReg and vuVCCReg only have one element. Paul Holden 2023-08-12 09:24:50 +01:00
  • e7e7d7c771 Use u16 for VMRG. Paul Holden 2023-08-12 09:14:36 +01:00
  • ec6f48741b Implement VCR. Paul Holden 2023-08-12 09:14:09 +01:00
  • b7103b2907 Implement VMRG. Paul Holden 2023-08-11 20:56:53 +01:00
  • 6bd8b26efb Merge and simplify the clamp functions. Paul Holden 2023-08-11 09:56:27 +01:00
  • 5bd25f2c3c Fix VMUDH. Paul Holden 2023-08-11 09:21:04 +01:00
  • c1510a4c3a Fix typo. Paul Holden 2023-08-11 09:01:54 +01:00
  • 9913fbb535 Disassembly for VMOV and the "VZERO" instructions. Paul Holden 2023-08-11 09:00:18 +01:00
  • b32466efad Fix element for VRCPH and VRSQH. Paul Holden 2023-08-10 23:12:36 +01:00
  • e14e076348 Format Paul Holden 2023-08-10 23:07:31 +01:00
  • 46d5020c01 Implement more instructions which just zero the target vector. Paul Holden 2023-08-10 22:59:44 +01:00
  • 9085d9f061 Import rsq16. Paul Holden 2023-08-10 22:58:24 +01:00
  • 3013685685 Don't log the table. Paul Holden 2023-08-10 22:26:55 +01:00
  • 9dbdeb5e92 Implement VRSQ, VRSQL, VRSQH. Paul Holden 2023-08-10 22:23:54 +01:00
  • a09c94e17d Fix VRCPL. Paul Holden 2023-08-10 09:17:32 +01:00
  • 2b25f92378 Fix VRCP dissassembly (it's not a inverse square root). Paul Holden 2023-08-10 09:14:43 +01:00
  • ae7e8bec97 Implement VRCPL and VRCPH. Paul Holden 2023-08-10 00:00:12 +01:00
  • 1c65424138 Improve comments for rcp16. Paul Holden 2023-08-09 21:53:45 +01:00
  • 49259d23b4 Implement VRCP. Paul Holden 2023-08-09 13:04:36 +01:00
  • fb6fbe028a Implement VMACQ. Paul Holden 2023-08-08 22:50:22 +01:00
  • 0ba80a4483 Tidy. Paul Holden 2023-08-08 22:49:38 +01:00
  • 7f064aa90a Implement VRNDN. Paul Holden 2023-08-08 09:18:04 +01:00
  • 0a2472949c Implement VMACF and VMACU. Paul Holden 2023-08-08 00:09:07 +01:00
  • eb16f60c13 Implement VAND, VNAND, VOR, VNOR, VXOR, VNXOR, VNOP Paul Holden 2023-08-07 23:53:14 +01:00
  • 3f31799808 Implement VLT, VEQ, VNE, VGE. Paul Holden 2023-08-07 23:41:55 +01:00
  • fd02114c71 Implement VABS. Paul Holden 2023-08-07 23:08:38 +01:00
  • 3fab2afa55 Implement VSUM (also 'vec zero' op). Paul Holden 2023-08-07 22:37:07 +01:00
  • 1f1c0c99ea Implement VADDB, VACCB, VSUCB, VSAD, VSAC (all 'vec zero' ops). Paul Holden 2023-08-07 22:35:47 +01:00
  • 95a13596d1 Implement VADDC. Paul Holden 2023-08-07 22:31:06 +01:00
  • c93e106158 Implement VSUB, VSUT, VSUBC, VSUBB. Paul Holden 2023-08-07 22:24:09 +01:00
  • 84729a0ca1 Implement VMULU, VRNDP, VMULQ, VMUDL, VMUDM, VMUDN, VMADL, VMADM, VMADH. Paul Holden 2023-08-07 13:03:58 +01:00
  • 29c44a2ab8 Fix VRNDP disassembly. Paul Holden 2023-08-07 08:41:20 +01:00
  • 68da2313dd Tidy Paul Holden 2023-08-07 00:03:44 +01:00
  • 3585965798 Implement VMULF. Paul Holden 2023-08-06 23:53:54 +01:00
  • 7e75c11f3b Increase safety limit. Paul Holden 2023-08-06 23:53:31 +01:00
  • 684e45342b Implement VMUDH, VMADN, VADD, VSAR. Paul Holden 2023-08-06 23:39:01 +01:00
  • 4e09435618 Add disassembly for some vector ops. Paul Holden 2023-08-06 23:12:05 +01:00
  • 61df6d685f Fix cop2 instruction decode. Paul Holden 2023-08-06 10:46:07 +01:00
  • c37c1507e0 Make the temp vector general purpose. Paul Holden 2023-08-06 09:32:08 +01:00
  • 3b3ae6fd3e Split up opcode for LWC2/SWC2 and COP2. Paul Holden 2023-08-06 09:31:47 +01:00
  • 21703641f9 Implement LTV. Paul Holden 2023-08-05 23:58:09 +01:00
  • 632c3c5ae2 Implement LFV. Paul Holden 2023-08-05 20:15:59 +01:00
  • 09f6ead752 Implement LPV, LUV, LHV. Paul Holden 2023-08-05 15:56:54 +01:00
  • bc3e6c5053 Implement LPV. Paul Holden 2023-08-05 15:48:20 +01:00
  • d486afe780 Fix LQV and SQV at end of dmem. Paul Holden 2023-08-05 15:09:16 +01:00
  • 5f9a989197 Implement MFC2 and MTC2. Paul Holden 2023-08-05 14:54:46 +01:00
  • f7864fa0bf Implement CFC2/CTC2. Paul Holden 2023-08-05 14:13:03 +01:00
  • 0a0e0b7b72 Fix CFC2/CTC2 disassembly - reg 3 is treated as VCE. Paul Holden 2023-08-05 14:11:05 +01:00
  • a1ab3c2bb9 Tidy comment. Paul Holden 2023-08-05 13:38:22 +01:00
  • 5bd3dd9412 Implement STV. Paul Holden 2023-08-05 13:27:07 +01:00
  • 3bfb13c20c Assert element index is in bounds. Paul Holden 2023-08-05 10:27:33 +01:00
  • 75682a99d4 Implement SWV. Paul Holden 2023-08-05 10:23:27 +01:00
  • 6a20c7cb1d Implement SFV. Paul Holden 2023-08-05 09:49:25 +01:00
  • 967215a633 Implement SPV, SUV and SHV. Paul Holden 2023-08-04 23:59:06 +01:00
  • e4fc415ba6 Stores should wrap. Paul Holden 2023-08-04 13:39:42 +01:00
  • 5dd4e6d6ec Tidy Paul Holden 2023-08-04 13:39:22 +01:00
  • a35a105c0e Implement LBV, LSV, LLV, LDV, LQV, LRV, SBV, SSV, SLV, SDV, SQV, SRV. Paul Holden 2023-08-04 13:39:14 +01:00
  • f885bf9441 Fix disassembly for vector stores and loads. Paul Holden 2023-08-04 13:34:35 +01:00
  • 20fd66a359 Add some missing vector ops. Paul Holden 2023-08-03 21:30:22 +01:00
  • 1091bce4aa Initial RSP implementation. Paul Holden 2023-08-03 20:41:26 +01:00
  • e5f3c8c7d2 Split out writeReg so it can be called from the RSP. Paul Holden 2023-08-03 20:31:27 +01:00
  • 107763f3be Include the address in the disassembly. Paul Holden 2023-08-02 23:54:02 +01:00
  • bcda2fae25 Don't worry about special handling for NOP. Paul Holden 2023-08-01 23:33:22 +01:00
  • 124889a371 RPS disassembly improvements. Paul Holden 2023-08-01 23:03:48 +01:00
  • 8b11f49876 Add accessors with base+offset names. Paul Holden 2023-08-01 08:59:54 +01:00
  • 8d70ac472b Add a disassembler for the RSP. Paul Holden 2023-07-31 22:58:51 +01:00
  • 2f4c37134a Stub out RSP. Paul Holden 2023-07-31 08:48:34 +01:00
  • 81e32232bb Return whether HLE happened so we can run LLE for unhandled tasks. Paul Holden 2023-07-31 08:38:28 +01:00
  • e33cf2838c Fix out of bounds access in moveMemLight. Paul Holden 2023-07-31 08:31:36 +01:00
  • 798831fee9 SP PC register masking. Paul Holden 2023-07-31 08:28:14 +01:00