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  • 7c353e55f1 Perform LW load even if the result isn't stored to trigger any exceptions. Paul Holden 2023-07-27 22:26:52 +01:00
  • 2889e65d32 Add an explicit pageMaskLowBits constant. Paul Holden 2023-07-27 22:15:36 +01:00
  • 38de1f29c4 Fix dynarec for cop1 instructions - these can raise exceptions. Paul Holden 2023-07-27 12:24:16 +01:00
  • 3561de7a51 Remove raiseX helpers and just use raiseException. Paul Holden 2023-07-27 12:20:27 +01:00
  • 85b57096be Add address helpers for dynarec. Paul Holden 2023-07-27 12:00:26 +01:00
  • 1acfaa5fa9 Expose some cop1 functions for dynarec. Paul Holden 2023-07-27 11:58:17 +01:00
  • a265576d44 Remove accessors for high parts of registers (unused now). Paul Holden 2023-07-27 11:02:54 +01:00
  • 8920b56702 Display registers using bigints. Paul Holden 2023-07-27 11:02:10 +01:00
  • 350c14924f Add helpers to compute reg[base]+offset. Paul Holden 2023-07-27 10:59:22 +01:00
  • 8005d63e11 Move memory access helpers out to a separate module. Paul Holden 2023-07-27 10:39:30 +01:00
  • edf8c1f6ee Always pass unsigned values to the 'slow' helpers. Paul Holden 2023-07-27 10:18:59 +01:00
  • 8211ce94fe Add 'fast' suffix to fast access routines. Paul Holden 2023-07-27 09:12:10 +01:00
  • 265a945e8a Rename MemoryRegion functions to get/set. Paul Holden 2023-07-27 09:01:02 +01:00
  • d63af9fd72 Split logging functionality out into a separate class. Paul Holden 2023-07-26 23:57:29 +01:00
  • 57d8431025 Use the Device implementation of readU64 and write64. Paul Holden 2023-07-26 23:44:46 +01:00
  • dbce637f4b Provide separate functions for calculating the EA for reads and writes. Paul Holden 2023-07-26 23:42:40 +01:00
  • 7f47761c40 Simplify MappedMemDevice accessors. Paul Holden 2023-07-26 23:03:31 +01:00
  • 74155e823b Call setBigUint64 directly from store64. Paul Holden 2023-07-26 18:08:18 +01:00
  • de7fe24820 Remove an old/invalid FIXME. Paul Holden 2023-07-26 18:07:25 +01:00
  • 69c6e9f2bf Implement store32masked in the Device and add a store64masked. Paul Holden 2023-07-26 18:06:37 +01:00
  • 6ee951100d Add some more helpers to MemoryRegion. Paul Holden 2023-07-26 17:53:49 +01:00
  • 0ad3df5167 Implement loadU64 similarly to other functions. Paul Holden 2023-07-26 16:18:58 +01:00
  • ab86e7e1d0 Add some notes. Paul Holden 2023-07-26 13:38:52 +01:00
  • 0186fb9936 Consolidate all the memory accessors in r4300.js. Paul Holden 2023-07-26 11:02:06 +01:00
  • f98e42faf7 Tidy presentBackBuffer. Paul Holden 2023-07-26 09:30:42 +01:00
  • e76b88e16e Push alignment further down memory handling callstack. Paul Holden 2023-07-25 22:57:05 +01:00
  • da383a675d Implement LWL, LWR, LDL, LDR, SWL, SWL, SDL, SDR using masked writes. Paul Holden 2023-07-25 19:23:32 +01:00
  • 91e0cf82b9 Use gprU32 for setRegU32Extend. Paul Holden 2023-07-25 19:08:27 +01:00
  • cf218adf2e Handle KSSEG and KSEG3 ranges. Paul Holden 2023-07-25 15:17:28 +01:00
  • 2a07b1ecc9 Handle status register similar to other control registers. Paul Holden 2023-07-25 15:11:18 +01:00
  • 8245a1a892 Fix SRAM. Paul Holden 2023-07-25 11:34:02 +01:00
  • 04fb88d9cc Ignore the branch delay when executing a TLB exception. Paul Holden 2023-07-24 20:47:50 +01:00
  • 4e5c8396e3 Fix random reg behaviour when wired >= 32. Paul Holden 2023-07-24 16:33:13 +01:00
  • 6d58c9659e Improve pagemask handling. Paul Holden 2023-07-24 16:01:29 +01:00
  • e7b0103ac7 Set XContext for TLB exceptions and clear CE bits. Paul Holden 2023-07-24 14:54:36 +01:00
  • 032e5c320e Set XContext for TLB exceptions and clear CE bits. Paul Holden 2023-07-24 13:39:02 +01:00
  • 42bc2d6061 Implement AdEl xcontext using 64 bits. Paul Holden 2023-07-23 23:57:11 +01:00
  • c0736b56bb EPC should be sign extended. Paul Holden 2023-07-23 23:56:28 +01:00
  • de17b23f40 Fix config register masking. Paul Holden 2023-07-23 23:23:46 +01:00
  • 662940e32a Fix EntryHi mask. Paul Holden 2023-07-23 23:02:15 +01:00
  • b3d21c2198 Implement DMTC0 and DMFC0 using 64 bits. Paul Holden 2023-07-23 22:58:44 +01:00
  • 9a512da4c3 Make the control registers 64 bit. Paul Holden 2023-07-23 22:37:35 +01:00
  • 60a22ae9da Rename control register members. Paul Holden 2023-07-23 22:31:32 +01:00
  • b816777861 Update some generated code to use control reg accessors. Paul Holden 2023-07-23 22:31:12 +01:00
  • c73d532c27 Tidy setTLB - no need to pass 'this' as an argument. Paul Holden 2023-07-23 22:30:39 +01:00
  • 07bde89eea Use accessor for incrementing count. Paul Holden 2023-07-23 22:25:53 +01:00
  • b44465f1cb Accessors for control registers. Paul Holden 2023-07-23 22:23:48 +01:00
  • 999b924453 Split out a moveToControl helper and call from MTC0 and DMTC0. Paul Holden 2023-07-23 14:26:06 +01:00
  • e0e64109ea Tidy Paul Holden 2023-07-23 14:23:29 +01:00
  • b8c8b36744 Mask writes to EntryHi. Paul Holden 2023-07-23 14:20:30 +01:00
  • 3d537c8025 Use nextpc+4 as the link address rather than pc+8. Paul Holden 2023-07-23 08:27:57 +01:00
  • dd7634fcf1 Keep track of the nextPC in FragmentContext. Paul Holden 2023-07-23 08:19:42 +01:00
  • a635eb40be Simplify how nextPC is set. Paul Holden 2023-07-23 07:58:25 +01:00
  • 9d13fe284a Ignore a local notes file I don't want to check in. Paul Holden 2023-07-23 07:52:21 +01:00
  • 786a500d38 Implement cart write behaviour. Paul Holden 2023-07-22 22:28:46 +01:00
  • 6f489bfc04 Implement broken LH/LB cart reads. Paul Holden 2023-07-22 21:49:51 +01:00
  • dbf69efa19 Throw AdEl exception on misaligned instruction fetch. Paul Holden 2023-07-22 17:49:08 +01:00
  • e9d36120f9 Ensure pc is treated as a signed value so the fastpath works. Paul Holden 2023-07-22 17:47:37 +01:00
  • e8d7029d3a Implement CachedMemDevice using DataView. Paul Holden 2023-07-22 17:46:39 +01:00
  • 9c16c19cfd Reimplement memory access to use dataviews. Paul Holden 2023-07-22 17:19:23 +01:00
  • fbaa417a19 Get the DataView from the MemoryRegion. Paul Holden 2023-07-22 08:39:43 +01:00
  • 15a17afbb7 s32 buffer is only used by CachedMemDevice. Paul Holden 2023-07-22 08:35:07 +01:00
  • 8481a04545 Use a DataView rather than bittwiddling. Paul Holden 2023-07-22 08:25:44 +01:00
  • 05f9d47c27 Don't format values if they're not logged. Paul Holden 2023-07-22 08:22:55 +01:00
  • eee8f2d13c Fix PIRamDevice readU8. Paul Holden 2023-07-22 08:13:03 +01:00
  • 45bfaaea41 SPMem is accessible from 0xa4000000 to 0xa4040000, but wraps every 0x2000 bytes. Paul Holden 2023-07-22 08:12:25 +01:00
  • 9443bb32af Tidy Paul Holden 2023-07-22 07:23:13 +01:00
  • 245a811088 Implement LLD using setRegU64. Paul Holden 2023-07-21 15:34:43 +01:00
  • 9f74b540e3 Implement generateOR and generateNOR using 64 bit instructions. Paul Holden 2023-07-21 15:31:27 +01:00
  • b5d9f2fcd5 Implement MFHI, MFLO, MTHI, MTLO using 64 bit moves. Paul Holden 2023-07-21 15:26:02 +01:00
  • d10a7ca8e0 Rename sourceBits etc to sBits. Paul Holden 2023-07-21 15:07:10 +01:00
  • 4a81400fee Reorder methods. Paul Holden 2023-07-21 15:04:38 +01:00
  • ec5fc5b14c Tidy cpu1 64 bit reg handling. Paul Holden 2023-07-21 15:02:57 +01:00
  • d51a3d7206 Rename store_i64_bigint to storeU64. Paul Holden 2023-07-21 14:43:03 +01:00
  • 73247185b4 Rename load_i32, load_f32, load_f64. Remove load_i64_number. Paul Holden 2023-07-21 14:42:02 +01:00
  • d19e42944c Rename store_f32 and store_f64. Paul Holden 2023-07-21 14:37:16 +01:00
  • 4fc4bc65bd store_64_hi_lo is unused. Paul Holden 2023-07-21 14:35:17 +01:00
  • 4647da07cd Implement store_i64_bigint by directly writing to BigUint64Array. Paul Holden 2023-07-21 14:34:42 +01:00
  • 39aece1e73 Implement LD and LDC1 using load_u64_bigint. Paul Holden 2023-07-21 14:31:02 +01:00
  • 36748af5ce Fix cpu1 regnames. Paul Holden 2023-07-21 14:30:00 +01:00
  • 3f16235a04 Remove store_i64_number (unused). Paul Holden 2023-07-21 14:22:35 +01:00
  • b0ed4761ab Rename store_i32 to storeS32. Paul Holden 2023-07-21 14:21:33 +01:00
  • 8fe816b5b2 Add regS64 and regU64. Zero the entire register. Paul Holden 2023-07-21 14:19:21 +01:00
  • d14e3dc5b1 Rename CPU1 registers. Paul Holden 2023-07-21 14:17:33 +01:00
  • 176e2d2218 Implement branches using BigInt. Paul Holden 2023-07-21 13:30:28 +01:00
  • 6d64a113b1 Use camelCase for naming locals. Paul Holden 2023-07-21 13:09:14 +01:00
  • 3ebfab7c89 Tidy SDC1. Paul Holden 2023-07-21 13:07:33 +01:00
  • 7ca5a10951 Use BigIntArray to store results from DIV, DIVU, DDIV, DDIVU. Paul Holden 2023-07-21 13:03:30 +01:00
  • c8ad802272 Store DMULT/DMULTU results using BigIntArray. Paul Holden 2023-07-21 12:56:08 +01:00
  • f931df95a1 Add BigInt64Arrays for multlo/multhi and write results from MULT and MULTU without shifts. Paul Holden 2023-07-21 12:50:06 +01:00
  • b5ebd0ca51 Rename multHi/multLo for consistency with other naming. Paul Holden 2023-07-21 07:30:16 +01:00
  • 26af33f2e8 Implement SLT using BigInt. Paul Holden 2023-07-21 07:14:28 +01:00
  • 00ca18fbc5 Implement SLTIU using BigInt. Paul Holden 2023-07-21 07:11:16 +01:00
  • 00cb37323a Implement XORI using BigInt. Paul Holden 2023-07-20 14:59:47 +01:00
  • 9ab66694d0 Implement ANDI using BigInt. Paul Holden 2023-07-20 14:57:12 +01:00
  • 8d2b6ac468 Implement ORI using BigInt. Paul Holden 2023-07-20 14:45:49 +01:00
  • 169cf1e9c5 Implement AND, OR, XOR, NOR using BigInt. Paul Holden 2023-07-20 14:41:38 +01:00
  • 26ce8f08b7 Rename setGPR_s64_lo_hi to setRegS64LoHi. Paul Holden 2023-07-20 14:35:33 +01:00
  • 99563e6063 Rename setGPR_s32_lo to setRegS32Lo. Paul Holden 2023-07-20 14:34:16 +01:00
  • d5082e25cc Rename setGPR_s32_signed to setRegS32Extend. Paul Holden 2023-07-20 14:33:10 +01:00