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  • 3612c62208 Format Paul Holden 2023-08-10 23:07:31 +01:00
  • 6360974209 Implement more instructions which just zero the target vector. Paul Holden 2023-08-10 22:59:44 +01:00
  • bee7f89fc9 Import rsq16. Paul Holden 2023-08-10 22:58:24 +01:00
  • 10af507fef Don't log the table. Paul Holden 2023-08-10 22:26:55 +01:00
  • e00fbaf024 Implement VRSQ, VRSQL, VRSQH. Paul Holden 2023-08-10 22:23:54 +01:00
  • c60ce09fe1 Fix VRCPL. Paul Holden 2023-08-10 09:17:32 +01:00
  • e24fbe7fd3 Fix VRCP dissassembly (it's not a inverse square root). Paul Holden 2023-08-10 09:14:43 +01:00
  • 344b87e69b Implement VRCPL and VRCPH. Paul Holden 2023-08-10 00:00:12 +01:00
  • b22984c1c0 Improve comments for rcp16. Paul Holden 2023-08-09 21:53:45 +01:00
  • 3d472357aa Implement VRCP. Paul Holden 2023-08-09 13:04:36 +01:00
  • 1b459aa65b Implement VMACQ. Paul Holden 2023-08-08 22:50:22 +01:00
  • a8fe790013 Tidy. Paul Holden 2023-08-08 22:49:38 +01:00
  • 256970cc13 Implement VRNDN. Paul Holden 2023-08-08 09:18:04 +01:00
  • ddf9fb748d Implement VMACF and VMACU. Paul Holden 2023-08-08 00:09:07 +01:00
  • 642c52fc6c Implement VAND, VNAND, VOR, VNOR, VXOR, VNXOR, VNOP Paul Holden 2023-08-07 23:53:14 +01:00
  • 7f8ad9d50a Implement VLT, VEQ, VNE, VGE. Paul Holden 2023-08-07 23:41:55 +01:00
  • e58bbe5802 Implement VABS. Paul Holden 2023-08-07 23:08:38 +01:00
  • 46c37e5325 Implement VSUM (also 'vec zero' op). Paul Holden 2023-08-07 22:37:07 +01:00
  • 8b76c2251d Implement VADDB, VACCB, VSUCB, VSAD, VSAC (all 'vec zero' ops). Paul Holden 2023-08-07 22:35:47 +01:00
  • 2385184c41 Implement VADDC. Paul Holden 2023-08-07 22:31:06 +01:00
  • caade0c531 Implement VSUB, VSUT, VSUBC, VSUBB. Paul Holden 2023-08-07 22:24:09 +01:00
  • 40f1a2231c Implement VMULU, VRNDP, VMULQ, VMUDL, VMUDM, VMUDN, VMADL, VMADM, VMADH. Paul Holden 2023-08-07 13:03:58 +01:00
  • 47daa65dda Fix VRNDP disassembly. Paul Holden 2023-08-07 08:41:20 +01:00
  • 8a83d0af9f Tidy Paul Holden 2023-08-07 00:03:44 +01:00
  • 2374dd9b6e Implement VMULF. Paul Holden 2023-08-06 23:53:54 +01:00
  • 2ba93bb14e Increase safety limit. Paul Holden 2023-08-06 23:53:31 +01:00
  • ab92321296 Implement VMUDH, VMADN, VADD, VSAR. Paul Holden 2023-08-06 23:39:01 +01:00
  • f2175e1691 Add disassembly for some vector ops. Paul Holden 2023-08-06 23:12:05 +01:00
  • 1477007aac Fix cop2 instruction decode. Paul Holden 2023-08-06 10:46:07 +01:00
  • 634e04a8f8 Make the temp vector general purpose. Paul Holden 2023-08-06 09:32:08 +01:00
  • 24af7b5fe4 Split up opcode for LWC2/SWC2 and COP2. Paul Holden 2023-08-06 09:31:47 +01:00
  • 04635f0e3e Implement LTV. Paul Holden 2023-08-05 23:58:09 +01:00
  • a4fac1cc55 Implement LFV. Paul Holden 2023-08-05 20:15:59 +01:00
  • 5a78075a56 Implement LPV, LUV, LHV. Paul Holden 2023-08-05 15:56:54 +01:00
  • 40a9156cfb Implement LPV. Paul Holden 2023-08-05 15:48:20 +01:00
  • fb6a4c684f Fix LQV and SQV at end of dmem. Paul Holden 2023-08-05 15:09:16 +01:00
  • 4421750ced Implement MFC2 and MTC2. Paul Holden 2023-08-05 14:54:46 +01:00
  • f5f1cb65db Implement CFC2/CTC2. Paul Holden 2023-08-05 14:13:03 +01:00
  • f4443ed612 Fix CFC2/CTC2 disassembly - reg 3 is treated as VCE. Paul Holden 2023-08-05 14:11:05 +01:00
  • bf77dcdaa9 Tidy comment. Paul Holden 2023-08-05 13:38:22 +01:00
  • a107848ba9 Implement STV. Paul Holden 2023-08-05 13:27:07 +01:00
  • 95d520ff07 Assert element index is in bounds. Paul Holden 2023-08-05 10:27:33 +01:00
  • db20ce1198 Implement SWV. Paul Holden 2023-08-05 10:23:27 +01:00
  • dcd5f60981 Implement SFV. Paul Holden 2023-08-05 09:49:25 +01:00
  • 9b830700a1 Implement SPV, SUV and SHV. Paul Holden 2023-08-04 23:59:06 +01:00
  • d221a2ec9f Stores should wrap. Paul Holden 2023-08-04 13:39:42 +01:00
  • 93822c6099 Tidy Paul Holden 2023-08-04 13:39:22 +01:00
  • 403cccb43e Implement LBV, LSV, LLV, LDV, LQV, LRV, SBV, SSV, SLV, SDV, SQV, SRV. Paul Holden 2023-08-04 13:39:14 +01:00
  • 68066ba5c1 Fix disassembly for vector stores and loads. Paul Holden 2023-08-04 13:34:35 +01:00
  • 9ec65b40f8 Add some missing vector ops. Paul Holden 2023-08-03 21:30:22 +01:00
  • 2bc16a89a9 Initial RSP implementation. Paul Holden 2023-08-03 20:41:26 +01:00
  • b71825f410 Split out writeReg so it can be called from the RSP. Paul Holden 2023-08-03 20:31:27 +01:00
  • 00c3efca54 Include the address in the disassembly. Paul Holden 2023-08-02 23:54:02 +01:00
  • d968ccd709 Don't worry about special handling for NOP. Paul Holden 2023-08-01 23:33:22 +01:00
  • 444b339a28 RPS disassembly improvements. Paul Holden 2023-08-01 23:03:48 +01:00
  • 8543559c27 Add accessors with base+offset names. Paul Holden 2023-08-01 08:59:54 +01:00
  • 74f7ca82c9 Add a disassembler for the RSP. Paul Holden 2023-07-31 22:58:51 +01:00
  • 032502897e Stub out RSP. Paul Holden 2023-07-31 08:48:34 +01:00
  • 56f7c09937 Return whether HLE happened so we can run LLE for unhandled tasks. Paul Holden 2023-07-31 08:38:28 +01:00
  • 6a156bc8f2 Fix out of bounds access in moveMemLight. Paul Holden 2023-07-31 08:31:36 +01:00
  • 28c28c3564 SP PC register masking. Paul Holden 2023-07-31 08:28:14 +01:00
  • 192fa9f490 Remove newline. Paul Holden 2023-07-30 22:52:59 +01:00
  • c1c777b65d Fix generateCTC1Stub. Paul Holden 2023-07-30 22:52:47 +01:00
  • f7fad1229d Detect underflow for D->S. Paul Holden 2023-07-30 22:07:21 +01:00
  • 0e09725e6b Tidy Paul Holden 2023-07-30 22:06:41 +01:00
  • 1c4508bd0e Set inexact for W->S and L->S. Paul Holden 2023-07-30 22:05:57 +01:00
  • 3f012c379f Convert function improvements. Paul Holden 2023-07-30 21:15:31 +01:00
  • a0d45dc788 cop1 half mode fixes. Paul Holden 2023-07-30 16:44:10 +01:00
  • 3dcbc340e2 Fix cart writing with offsets. Paul Holden 2023-07-30 00:41:15 +01:00
  • 368c74fb19 Fix parity error register masking. Paul Holden 2023-07-30 00:34:27 +01:00
  • 61df9e4070 Writes to fpcsr31 should be masked. Paul Holden 2023-07-30 00:27:51 +01:00
  • e1cd27f370 FCR0 should be 0xa00. Paul Holden 2023-07-30 00:24:15 +01:00
  • fac0530026 CTC1 can trigger FPE on writes. Paul Holden 2023-07-30 00:16:42 +01:00
  • c0faabcb29 Only the bottom 32 llAddr bits are writable. Paul Holden 2023-07-30 00:16:21 +01:00
  • 42b5a7fd4c Explicitly handle ErrorEPC. Paul Holden 2023-07-29 23:59:00 +01:00
  • 63b3692b48 Fix writes to XContext - it's masked to upper bits and MTC0 should sign extend. Paul Holden 2023-07-29 23:58:43 +01:00
  • 02996adf19 Fix executeSetRDPOtherMode (accessing undefined vars). Paul Holden 2023-07-29 23:41:33 +01:00
  • 0827f8a9fa Ignore writes to R0 via register accessors. Paul Holden 2023-07-29 23:40:26 +01:00
  • dffaa293a6 setRegS32Lo is unused. Paul Holden 2023-07-29 23:33:24 +01:00
  • e09f89b023 Use unsigned PC in dynarec code. Paul Holden 2023-07-29 23:30:45 +01:00
  • 0891e3f9aa Add debugging code to validate the dynarec pc. Paul Holden 2023-07-29 23:30:18 +01:00
  • e8ea885791 Bug fix for dynarec assembling into fragments which were previously interrupted. Paul Holden 2023-07-29 23:23:43 +01:00
  • 57ddd3da61 Make sure comments end in newlines. Paul Holden 2023-07-29 23:20:38 +01:00
  • 8a2551b5c8 Set branchDelay whether the branch is take or not. Paul Holden 2023-07-29 17:10:46 +01:00
  • 17214c41ae Make sure generated code ends in a newline. Paul Holden 2023-07-29 17:01:54 +01:00
  • 0066592702 Automatically add newlines to generated code as needed. Paul Holden 2023-07-29 14:25:25 +01:00
  • 72d485d288 Reorder functions. Paul Holden 2023-07-29 14:02:33 +01:00
  • 7bb8c89f6c Simplify generateGenericOpBoilerplate. Paul Holden 2023-07-29 14:01:21 +01:00
  • 3b7ab06448 Improve SP accuracy. Paul Holden 2023-07-29 11:45:25 +01:00
  • c3a9768836 Emulate broken SB, SH, SD for spmem. Paul Holden 2023-07-29 09:11:10 +01:00
  • e7f177c86b Fix Paul Holden 2023-07-29 09:02:02 +01:00
  • 6555e96646 Fix PIF memory SH and SB. Paul Holden 2023-07-29 08:59:11 +01:00
  • 6994ceb0d8 Remove pif prefix. Paul Holden 2023-07-28 10:48:44 +01:00
  • f40d44dae7 Set the global bit consistently between pfne/o when setting the TLB entry. Paul Holden 2023-07-28 10:30:06 +01:00
  • e16d292cb6 Tidy code for raising TLB and AdEl exceptions. Paul Holden 2023-07-28 10:17:31 +01:00
  • 2475491780 Implement entryHi as a 64 bit register. Paul Holden 2023-07-28 09:32:17 +01:00
  • 38aa41261b vpn2mask doesn't need to be stored. Paul Holden 2023-07-27 22:47:37 +01:00
  • 27f04dddbe Init TLBEntry fields in the constructor. Paul Holden 2023-07-27 22:38:11 +01:00
  • 3bcbe4f8c7 Get rid of mask2 and compute it directly. Paul Holden 2023-07-27 22:34:42 +01:00
  • 0e1d2fa0a6 Raise a TLB Mod exception if the dirty bit is clear. Paul Holden 2023-07-27 22:30:41 +01:00