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  • a06c721280 Add generateBreakpoint. Paul Holden 2023-08-20 18:25:24 +01:00
  • 6ec0665522 Add generateUnknown. Paul Holden 2023-08-20 18:21:40 +01:00
  • 78bbc776e7 Generate the remaining regimm instructions. Paul Holden 2023-08-20 15:20:34 +01:00
  • 5a15ce33a5 Just use this. Paul Holden 2023-08-20 15:19:55 +01:00
  • 382eb603aa Generate TGEI etc. Paul Holden 2023-08-20 15:10:47 +01:00
  • f8547fa6ce Stub out missing load/store to coprocessor instructions. Paul Holden 2023-08-20 15:01:25 +01:00
  • 56ae6ca850 Step RSP from dynarec. Paul Holden 2023-08-20 14:32:14 +01:00
  • 0e34e5ff49 Generate LL, SC etc. Paul Holden 2023-08-20 14:11:16 +01:00
  • e4ceed3259 Inline simpleTable instructions. Paul Holden 2023-08-19 16:35:38 +01:00
  • 5ad40624e0 Add generators for the cop1 move instructions. Paul Holden 2023-08-19 16:14:43 +01:00
  • 2f595bad1e Add generators for the cop2 instructions. Paul Holden 2023-08-19 15:49:57 +01:00
  • 5d7cb4ae65 Move Cop0 code. Paul Holden 2023-08-19 15:49:22 +01:00
  • 7b949b25d6 Stub out cop2 and cop2 generation. Paul Holden 2023-08-19 15:36:44 +01:00
  • 9d06e24adb Remove some unused exports. Paul Holden 2023-08-19 14:02:44 +01:00
  • 13be8d4f81 Add generators for BLEZL and BGTZL. Paul Holden 2023-08-19 13:58:59 +01:00
  • 473c18bd77 Use template string. Paul Holden 2023-08-19 13:52:42 +01:00
  • 2b2d206288 Add generators for LWL etc. Paul Holden 2023-08-19 13:49:16 +01:00
  • 46f1d817c1 Add generators for the remaining cop0 instructions. Paul Holden 2023-08-19 13:41:46 +01:00
  • 4887c7a8c3 Inline special functions. Paul Holden 2023-08-19 13:31:43 +01:00
  • 66cd3e5a9b genCalcAddressS32 and genCalcAddressU32 are unused. Paul Holden 2023-08-19 13:30:52 +01:00
  • 9bfe68439f Decode+execute for LL/SC instructions. Paul Holden 2023-08-19 13:18:50 +01:00
  • 6c9b380ffa Dedupe code generation for CACHE. Paul Holden 2023-08-19 13:08:54 +01:00
  • 6357f6d4e4 Decode+execute for store instructions. Paul Holden 2023-08-19 13:01:57 +01:00
  • ea5c4b69d0 Decode+execute for load instructions. Paul Holden 2023-08-19 12:40:56 +01:00
  • f9ba51c8aa Decode+execute for SLTI/SLTIU/ANDI/ORI/XORI/LUI. Paul Holden 2023-08-19 12:17:40 +01:00
  • b97229d3b5 Decode+execute for ADDI + variants. Paul Holden 2023-08-19 09:08:27 +01:00
  • d2dd58045a Add generators for the remaining special instructions. Paul Holden 2023-08-19 08:46:50 +01:00
  • 070a5386e0 Format. Paul Holden 2023-08-19 08:23:19 +01:00
  • 859c010228 Split branch instructions into decode+execute. Paul Holden 2023-08-18 17:25:05 +01:00
  • ff0b7287b3 Convert MF/MTC0 and trap instructions into decode+execute parts. Paul Holden 2023-08-18 16:49:00 +01:00
  • b5ac075528 Convert some arithmetic instructions into decode+execute parts. Paul Holden 2023-08-18 06:38:48 +01:00
  • 1b36da938d Convert some arithmetic instructions into decode+execute parts. Paul Holden 2023-08-18 06:17:02 +01:00
  • 85fba36e96 Start to split instructions into separate functions to decode and execute. Paul Holden 2023-08-17 13:44:38 +01:00
  • 9517533dd1 Run JPG and VID tasks on the RSP. Paul Holden 2023-08-17 13:17:42 +01:00
  • 086a8de529 Improve interaction of stuffToDo when running the RSP. Paul Holden 2023-08-17 13:17:18 +01:00
  • e286516bdc Fix setCompare. Paul Holden 2023-08-17 10:44:58 +01:00
  • 3570b5c380 Format Paul Holden 2023-08-17 10:43:19 +01:00
  • 24862c8fd6 Don't redraw debugger content when it's hidden. Paul Holden 2023-08-17 10:05:23 +01:00
  • 97d9a2940c Run the RSP in parallel to the CPU. Paul Holden 2023-08-17 08:38:29 +01:00
  • c24ec0b790 Remove logging about cache invalidation. Paul Holden 2023-08-17 08:25:29 +01:00
  • ca1dfe390f Take a deep reference to the SPIBIST registers to access the program counter. Paul Holden 2023-08-16 23:05:40 +01:00
  • 6d17d740f4 Use setControlU64 rather than moveToControl as the latter ignores writes to readonly registers. Paul Holden 2023-08-16 22:57:24 +01:00
  • c1f3804c7b Boundscheck reads and writes. Paul Holden 2023-08-16 22:47:33 +01:00
  • 81e4c3ee36 Raise AdEL or AdES exceptions for unaligned accesses. Paul Holden 2023-08-16 20:50:24 +01:00
  • 5c73de6537 Use the tvType from rominfo rather than switching on the country code. Paul Holden 2023-08-16 09:14:13 +01:00
  • c0ed7bb277 Format Paul Holden 2023-08-16 09:05:18 +01:00
  • 4c85e693e9 Pick up changes from https://github.com/hulkholden/daedalus/blob/master/Source/Core/ROM.cpp. Paul Holden 2023-08-16 09:04:56 +01:00
  • 1f312b90f4 Tidy Paul Holden 2023-08-16 08:47:52 +01:00
  • 3a8b5eef4f Fix boot for CIC x105. Paul Holden 2023-08-15 23:15:04 +01:00
  • fee5a54c0a Print whether it's the CPU or RSP executing an unknown op. Paul Holden 2023-08-15 09:12:44 +01:00
  • 743cdc1d9a Call reset() on all devices. Paul Holden 2023-08-14 22:02:34 +01:00
  • f246a87d9a BadVAddr should be sign extended. Paul Holden 2023-08-14 20:43:04 +01:00
  • 1c9266ba2f Halting through SP_SET_HALT shouldn't set BROKE. Paul Holden 2023-08-14 20:31:47 +01:00
  • 02a3c4188e Implement SP_SEMAPHORE_REG. Paul Holden 2023-08-14 20:22:09 +01:00
  • 5818f42c9a Both read and write length registers are set at the end of DMA transfer. Paul Holden 2023-08-14 20:08:04 +01:00
  • 13b2496c75 Fix setOrClear - should return original bits if neither set nor clear specified. Paul Holden 2023-08-14 20:06:17 +01:00
  • a7854377ff Fix SP status flags. Paul Holden 2023-08-14 09:06:26 +01:00
  • 3e49095d72 Don't run RSP if both SP_SET_HALT and SP_CLR_HALT are set. Paul Holden 2023-08-14 08:45:45 +01:00
  • 512ed82ea4 Fully implement moveFromControl and moveToControl. Paul Holden 2023-08-14 08:35:43 +01:00
  • f436d396f0 Merge vectorRecip and vectorRecipSqrt. Paul Holden 2023-08-14 00:03:47 +01:00
  • 75bb435d8c Tidy reciprocal functions. Paul Holden 2023-08-14 00:00:34 +01:00
  • 334630c92e Dedupe executeVRCPH and executeVRSQH. Paul Holden 2023-08-13 23:58:39 +01:00
  • 44945a60ae Fix arg order for vectorSetAccFromReg. Paul Holden 2023-08-13 23:56:18 +01:00
  • 04dce3449d Reorder functions. Paul Holden 2023-08-13 23:54:51 +01:00
  • 15a15ddc73 Add a vectorLogical helper. Paul Holden 2023-08-13 23:53:50 +01:00
  • 71ef24dd89 Init select in the loop initialiser. Paul Holden 2023-08-13 23:47:54 +01:00
  • 5167e2048f Use vectorSetAccFromReg helper. Paul Holden 2023-08-13 23:46:59 +01:00
  • 9583a5c493 Use setVecFromAccLow for VSUBC. Paul Holden 2023-08-13 23:46:23 +01:00
  • 6f1e0277f0 Use setVecFromAccLow for VADDC. Paul Holden 2023-08-13 23:46:11 +01:00
  • 06c504b4c8 Update VMRG to use setVecFromAccLow. Paul Holden 2023-08-13 23:39:15 +01:00
  • a99044c806 Update logical ops to use setVecFromAccLow. Paul Holden 2023-08-13 23:38:37 +01:00
  • 08a47910e0 Set the register directly from the accumulator. Paul Holden 2023-08-13 23:26:54 +01:00
  • 6f85f50baa Dedupe vectorSetAccFromReg. Paul Holden 2023-08-13 23:24:52 +01:00
  • 53ed8b206a Add some helpers to reduce duplication across vector multiply instructions. Paul Holden 2023-08-13 23:08:40 +01:00
  • c0938db49d Rename the main output result. Paul Holden 2023-08-13 22:25:24 +01:00
  • 09f315b7fa Add an accessor for setting the low accumulator bits. Paul Holden 2023-08-13 22:10:46 +01:00
  • d8345cdf4c Fix VCO shifting. Paul Holden 2023-08-13 21:51:25 +01:00
  • c292b569e2 Rename locals consistently. Paul Holden 2023-08-13 21:28:22 +01:00
  • 1d27c41799 Set the output directly from the accumulator regs in a separate pass. Paul Holden 2023-08-13 21:03:36 +01:00
  • 87761a92f1 Remove stray comment. Paul Holden 2023-08-13 17:03:05 +01:00
  • 12e4d8ae3c Inline accum48SignExtend. Paul Holden 2023-08-13 17:02:37 +01:00
  • be9495e6d3 Add some accessors to simplfy vector multiply ops. Paul Holden 2023-08-13 17:01:23 +01:00
  • a5d3a0f287 Get rid of newAccum temporary. Paul Holden 2023-08-13 15:22:14 +01:00
  • 66e4b411b9 Remove TODOs: this seems to be working correctly. Paul Holden 2023-08-13 15:19:33 +01:00
  • 839f64453c Emulate accumulator overflow correctly. Paul Holden 2023-08-13 15:16:20 +01:00
  • a0b71ef99e Implement VEXTT, VEXTQ, VEXTN, VINST, VINSQ, VINSN (all vectorZero). Paul Holden 2023-08-12 14:35:00 +01:00
  • 0e4124b2a7 Implement VNULL. Paul Holden 2023-08-12 14:26:10 +01:00
  • 40645b0676 Implement VCH. Paul Holden 2023-08-12 14:22:43 +01:00
  • 1d6ed54471 Tidy VCL. Paul Holden 2023-08-12 13:05:46 +01:00
  • df653e004f Implement VCL. Paul Holden 2023-08-12 13:03:04 +01:00
  • 879e49a318 Add accessors for VCC hi and lo bits. Paul Holden 2023-08-12 09:26:05 +01:00
  • 6dcf79429d vuVCOReg and vuVCCReg only have one element. Paul Holden 2023-08-12 09:24:50 +01:00
  • 737169d702 Use u16 for VMRG. Paul Holden 2023-08-12 09:14:36 +01:00
  • ce47167c4e Implement VCR. Paul Holden 2023-08-12 09:14:09 +01:00
  • 287f9d0088 Implement VMRG. Paul Holden 2023-08-11 20:56:53 +01:00
  • b58be2006e Merge and simplify the clamp functions. Paul Holden 2023-08-11 09:56:27 +01:00
  • a3fb614e44 Fix VMUDH. Paul Holden 2023-08-11 09:21:04 +01:00
  • da029913cf Fix typo. Paul Holden 2023-08-11 09:01:54 +01:00
  • a1e95b10b5 Disassembly for VMOV and the "VZERO" instructions. Paul Holden 2023-08-11 09:00:18 +01:00
  • 20ee99eb77 Fix element for VRCPH and VRSQH. Paul Holden 2023-08-10 23:12:36 +01:00