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  • 2a35f83255 s32 buffer is only used by CachedMemDevice. Paul Holden 2023-07-22 08:35:07 +01:00
  • fea6d487cf Use a DataView rather than bittwiddling. Paul Holden 2023-07-22 08:25:44 +01:00
  • 068dfe1396 Don't format values if they're not logged. Paul Holden 2023-07-22 08:22:55 +01:00
  • 0bf469b568 Fix PIRamDevice readU8. Paul Holden 2023-07-22 08:13:03 +01:00
  • f1ea11883d SPMem is accessible from 0xa4000000 to 0xa4040000, but wraps every 0x2000 bytes. Paul Holden 2023-07-22 08:12:25 +01:00
  • 79cc135707 Tidy Paul Holden 2023-07-22 07:23:13 +01:00
  • 4fe6b601ca Implement LLD using setRegU64. Paul Holden 2023-07-21 15:34:43 +01:00
  • ac1fc58674 Implement generateOR and generateNOR using 64 bit instructions. Paul Holden 2023-07-21 15:31:27 +01:00
  • 4e5faed89d Implement MFHI, MFLO, MTHI, MTLO using 64 bit moves. Paul Holden 2023-07-21 15:26:02 +01:00
  • 50e197da2d Rename sourceBits etc to sBits. Paul Holden 2023-07-21 15:07:10 +01:00
  • 36b21e458d Reorder methods. Paul Holden 2023-07-21 15:04:38 +01:00
  • e6c142df87 Tidy cpu1 64 bit reg handling. Paul Holden 2023-07-21 15:02:57 +01:00
  • b716262709 Rename store_i64_bigint to storeU64. Paul Holden 2023-07-21 14:43:03 +01:00
  • f837124293 Rename load_i32, load_f32, load_f64. Remove load_i64_number. Paul Holden 2023-07-21 14:42:02 +01:00
  • 0193cff714 Rename store_f32 and store_f64. Paul Holden 2023-07-21 14:37:16 +01:00
  • 57777532fb store_64_hi_lo is unused. Paul Holden 2023-07-21 14:35:17 +01:00
  • 8f2fce8b15 Implement store_i64_bigint by directly writing to BigUint64Array. Paul Holden 2023-07-21 14:34:42 +01:00
  • 3a0b92368c Implement LD and LDC1 using load_u64_bigint. Paul Holden 2023-07-21 14:31:02 +01:00
  • 32e2b51ad1 Fix cpu1 regnames. Paul Holden 2023-07-21 14:30:00 +01:00
  • 813dfc1cb1 Remove store_i64_number (unused). Paul Holden 2023-07-21 14:22:35 +01:00
  • 5b19ee49b5 Rename store_i32 to storeS32. Paul Holden 2023-07-21 14:21:33 +01:00
  • 86f2e3aa31 Add regS64 and regU64. Zero the entire register. Paul Holden 2023-07-21 14:19:21 +01:00
  • b978987fd8 Rename CPU1 registers. Paul Holden 2023-07-21 14:17:33 +01:00
  • c8a7c63873 Implement branches using BigInt. Paul Holden 2023-07-21 13:30:28 +01:00
  • f9c5221f27 Use camelCase for naming locals. Paul Holden 2023-07-21 13:09:14 +01:00
  • 1fc193b592 Tidy SDC1. Paul Holden 2023-07-21 13:07:33 +01:00
  • cab7e12a11 Use BigIntArray to store results from DIV, DIVU, DDIV, DDIVU. Paul Holden 2023-07-21 13:03:30 +01:00
  • 89d6ffebe8 Store DMULT/DMULTU results using BigIntArray. Paul Holden 2023-07-21 12:56:08 +01:00
  • cedba906d5 Add BigInt64Arrays for multlo/multhi and write results from MULT and MULTU without shifts. Paul Holden 2023-07-21 12:50:06 +01:00
  • 6e1b1c1db5 Rename multHi/multLo for consistency with other naming. Paul Holden 2023-07-21 07:30:16 +01:00
  • 700a90c780 Implement SLT using BigInt. Paul Holden 2023-07-21 07:14:28 +01:00
  • 7aab0895db Implement SLTIU using BigInt. Paul Holden 2023-07-21 07:11:16 +01:00
  • 7559b4e34c Implement XORI using BigInt. Paul Holden 2023-07-20 14:59:47 +01:00
  • 62175a6920 Implement ANDI using BigInt. Paul Holden 2023-07-20 14:57:12 +01:00
  • ebac030546 Implement ORI using BigInt. Paul Holden 2023-07-20 14:45:49 +01:00
  • 09b3d994b5 Implement AND, OR, XOR, NOR using BigInt. Paul Holden 2023-07-20 14:41:38 +01:00
  • a1a7b7b0be Rename setGPR_s64_lo_hi to setRegS64LoHi. Paul Holden 2023-07-20 14:35:33 +01:00
  • d79e489c3f Rename setGPR_s32_lo to setRegS32Lo. Paul Holden 2023-07-20 14:34:16 +01:00
  • 588cf43e82 Rename setGPR_s32_signed to setRegS32Extend. Paul Holden 2023-07-20 14:33:10 +01:00
  • ca4c5c98d6 Rename setGPR_s32_unsigned to setRegU32Extend. Paul Holden 2023-07-20 14:28:22 +01:00
  • 0c129a13c2 Tidy Paul Holden 2023-07-20 14:25:53 +01:00
  • 52a28469b2 Rename genSrcRegHi to genSrcRegS32Hi. Paul Holden 2023-07-20 14:23:55 +01:00
  • 05cd851892 Rename genSrcRegLo to genSrcRegS32Lo. Paul Holden 2023-07-20 14:22:34 +01:00
  • 8ed22f39d8 Rename getGPR_s32_signed to getRegS32Lo. Paul Holden 2023-07-20 14:21:10 +01:00
  • 288c85f421 Rename getGPR_s32_unsigned to getRegU32Lo. Paul Holden 2023-07-20 14:18:37 +01:00
  • 16bcc85755 Log bad pagemasks rather than halting. Paul Holden 2023-07-20 14:13:31 +01:00
  • 592f4275f5 Rename getGPR_s32_hi_signed to getRegS32Hi. Paul Holden 2023-07-20 14:12:01 +01:00
  • d9353b8c3b Rename getGPR_s32_hi_unsigned to getRegU32Hi. Paul Holden 2023-07-20 14:09:34 +01:00
  • 7909b9d78d Rename setGPR_s64_bigint to setRegU64. Paul Holden 2023-07-20 14:06:57 +01:00
  • 92ec14244e Tidy Paul Holden 2023-07-20 14:04:06 +01:00
  • 9809ec3797 Rename getGPR_u64_bigint to getRegU64. Paul Holden 2023-07-20 14:03:50 +01:00
  • 11f7311599 Rename getGPR_s64_bigint to getRegS64. Paul Holden 2023-07-20 13:57:08 +01:00
  • 1818713416 Add BigUint64Array so 64 bit values can be read directly. Paul Holden 2023-07-20 08:14:44 +01:00
  • 1707567f1d Interleave gprLo/Hi into a single array. Paul Holden 2023-07-20 08:11:10 +01:00
  • 6d56faf6eb Use register accessors. Paul Holden 2023-07-20 08:10:30 +01:00
  • e4a7173857 Clean up the last few uses of gprLo_signed. Paul Holden 2023-07-20 07:59:04 +01:00
  • 468344a626 Clean up last few direct uses of gprLo. Paul Holden 2023-07-20 07:54:38 +01:00
  • ebde3743a4 Use register accessors for LWL, LWR, SWL, SWR. Paul Holden 2023-07-20 07:50:57 +01:00
  • 66ff7291c3 Use register accessors for SLTI, SLTIU. Paul Holden 2023-07-20 07:49:41 +01:00
  • 88ee3d6879 Use register accessors for JALR, JR. Paul Holden 2023-07-20 07:48:22 +01:00
  • 671a2cd53b Remove memaddr Paul Holden 2023-07-20 07:16:36 +01:00
  • fe500fcbcf Force r0 to be zero. Paul Holden 2023-07-20 07:13:03 +01:00
  • 8d0c2334d4 Use register accessors for CFC1. Paul Holden 2023-07-20 07:09:23 +01:00
  • 3e9f340a24 Replace setSignExtend with cpu0.setGPR_s32_signed. Paul Holden 2023-07-20 07:08:06 +01:00
  • 2375e05bed Use register accessors for SB, SH, SW, SD. Paul Holden 2023-07-20 07:02:14 +01:00
  • 250dbd924f Use register accessors for LL, LLD, SC, SCD. Paul Holden 2023-07-20 06:56:39 +01:00
  • bfb8bd033a Use register accessors for LD. Paul Holden 2023-07-20 06:48:54 +01:00
  • 3f187d443a Use register accessors for ANDI, ORI, XORI. Paul Holden 2023-07-19 14:12:15 +01:00
  • b280172751 Use register accessors for SLTI and SLTIU. Paul Holden 2023-07-19 14:07:19 +01:00
  • b900192668 Use register accessors for MFHI and MFLO. Paul Holden 2023-07-19 14:04:30 +01:00
  • df0d349b8d Use register accessors for branches. Paul Holden 2023-07-19 14:02:58 +01:00
  • 1e75b78672 Implement SLT and SLTU using BigInt. Paul Holden 2023-07-19 13:56:59 +01:00
  • 0982698644 Use register accessors for AND, OR, XOR, NOR. Paul Holden 2023-07-19 13:50:55 +01:00
  • 7218f713fa Use register accessors for ADD, ADDU, SUB, SUBU. Paul Holden 2023-07-19 13:47:19 +01:00
  • d390906445 Use register accessors for DIV and DIVU. Paul Holden 2023-07-19 13:46:09 +01:00
  • 93b2da6f7e Use register accessors for MTHI, MTLO, MULT, MULTU. Paul Holden 2023-07-19 13:44:39 +01:00
  • 8cea65f316 Simplify DLLV, DSRLV, DSRAV using BigInt. Paul Holden 2023-07-19 13:43:41 +01:00
  • 82b71d3072 Simplify DSLL, DSRL, DSRA, DSLL32, DSRL32, DSRA32 using BigInt. Paul Holden 2023-07-19 13:39:05 +01:00
  • 83e0ea44dc Add a TODO. Paul Holden 2023-07-19 13:31:40 +01:00
  • 49993eb46a Tidy SLLV, SRLV, SRAV. Paul Holden 2023-07-19 11:56:41 +01:00
  • 9c8c1b0a48 Tidy SLL, SRL, SRA. Paul Holden 2023-07-19 11:50:23 +01:00
  • 5751671adb Add raiseAdELException. Paul Holden 2023-07-19 11:43:22 +01:00
  • 74876b6dba Change dynarec to access registers via CPU0 helpers. Paul Holden 2023-07-19 10:50:47 +01:00
  • dff130aa79 Implement SRA using BigInts. Paul Holden 2023-07-19 10:07:12 +01:00
  • d5bf8fd356 Add some helpers to encapsulate gprLo access. Paul Holden 2023-07-19 09:53:56 +01:00
  • f6ef7c1a26 Tidy DSLLV, DSRLV, DSRAV. Paul Holden 2023-07-19 09:50:31 +01:00
  • 855a973f2e Tidy CPU0 constructor. Paul Holden 2023-07-19 09:36:27 +01:00
  • 84c725cc3d Tidy MFC1, DMFC1, CMTC1 Paul Holden 2023-07-19 09:32:56 +01:00
  • 69109960aa Tidy SB, SH, SW, SD, SWC1, SDC1. Paul Holden 2023-07-19 09:23:24 +01:00
  • 69b8067367 Tidy LUI, LB, LBU, LH, LHU, LW, LWU. Paul Holden 2023-07-19 09:08:17 +01:00
  • b609c74e06 Tidy SLLV, SRLV, SRAV. Paul Holden 2023-07-19 08:58:45 +01:00
  • 9b568f1c65 Tidy SLL, SRL, SRA. Paul Holden 2023-07-19 08:56:19 +01:00
  • 96e8467c45 Implement integer overflow exceptions. Paul Holden 2023-07-18 23:47:17 +01:00
  • f1395a4426 Add cop2 and cop3 disassembly. Paul Holden 2023-07-18 23:43:44 +01:00
  • b784a74ed8 Fix toString64_bigint - this was truncating the bigints and we really want to see all of it. Paul Holden 2023-07-18 22:50:48 +01:00
  • d00dc177f2 Fix branch and link instructions - these should check the condition before updating the register. Paul Holden 2023-07-18 22:28:26 +01:00
  • f5effadf1b setZeroExtend is unused. Paul Holden 2023-07-18 21:52:49 +01:00
  • c9a0a3bfb6 Implement cop2 and cop3. Paul Holden 2023-07-18 21:52:17 +01:00
  • 319081564e MFC0 should sign extend. Paul Holden 2023-07-18 20:59:14 +01:00
  • e32ccb7e5a Tidy opcode initialisation. Paul Holden 2023-07-18 09:26:06 +01:00