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  • ae31057a93 Remove newline. Paul Holden 2023-07-30 22:52:59 +01:00
  • c35b8d531f Fix generateCTC1Stub. Paul Holden 2023-07-30 22:52:47 +01:00
  • dd996e1397 Detect underflow for D->S. Paul Holden 2023-07-30 22:07:21 +01:00
  • 8f4dfdd1dd Tidy Paul Holden 2023-07-30 22:06:41 +01:00
  • 701d464250 Set inexact for W->S and L->S. Paul Holden 2023-07-30 22:05:57 +01:00
  • 09f5afa2f1 Convert function improvements. Paul Holden 2023-07-30 21:15:31 +01:00
  • 0ffd40d35c cop1 half mode fixes. Paul Holden 2023-07-30 16:44:10 +01:00
  • 38e2d954d0 Fix cart writing with offsets. Paul Holden 2023-07-30 00:41:15 +01:00
  • 1be1d1ad25 Fix parity error register masking. Paul Holden 2023-07-30 00:34:27 +01:00
  • 1e8bbc269b Writes to fpcsr31 should be masked. Paul Holden 2023-07-30 00:27:51 +01:00
  • d4bc02c0c4 FCR0 should be 0xa00. Paul Holden 2023-07-30 00:24:15 +01:00
  • d567a77534 CTC1 can trigger FPE on writes. Paul Holden 2023-07-30 00:16:42 +01:00
  • 018ffe6595 Only the bottom 32 llAddr bits are writable. Paul Holden 2023-07-30 00:16:21 +01:00
  • 7076e0ac62 Explicitly handle ErrorEPC. Paul Holden 2023-07-29 23:59:00 +01:00
  • 8f6f2ac745 Fix writes to XContext - it's masked to upper bits and MTC0 should sign extend. Paul Holden 2023-07-29 23:58:43 +01:00
  • 5b6335eb72 Fix executeSetRDPOtherMode (accessing undefined vars). Paul Holden 2023-07-29 23:41:33 +01:00
  • 3ec1e0cfa0 Ignore writes to R0 via register accessors. Paul Holden 2023-07-29 23:40:26 +01:00
  • 17dee1735a setRegS32Lo is unused. Paul Holden 2023-07-29 23:33:24 +01:00
  • 04eb7d04d7 Use unsigned PC in dynarec code. Paul Holden 2023-07-29 23:30:45 +01:00
  • 5c43099064 Add debugging code to validate the dynarec pc. Paul Holden 2023-07-29 23:30:18 +01:00
  • bf401ed5dd Bug fix for dynarec assembling into fragments which were previously interrupted. Paul Holden 2023-07-29 23:23:43 +01:00
  • 3c6ffa40dc Make sure comments end in newlines. Paul Holden 2023-07-29 23:20:38 +01:00
  • 640a5cfe98 Set branchDelay whether the branch is take or not. Paul Holden 2023-07-29 17:10:46 +01:00
  • 27a9668843 Make sure generated code ends in a newline. Paul Holden 2023-07-29 17:01:54 +01:00
  • 4a74f10da2 Automatically add newlines to generated code as needed. Paul Holden 2023-07-29 14:25:25 +01:00
  • cb309f493d Reorder functions. Paul Holden 2023-07-29 14:02:33 +01:00
  • 6d2656282c Simplify generateGenericOpBoilerplate. Paul Holden 2023-07-29 14:01:21 +01:00
  • c3ac0d676e Improve SP accuracy. Paul Holden 2023-07-29 11:45:25 +01:00
  • 6b586231dc Emulate broken SB, SH, SD for spmem. Paul Holden 2023-07-29 09:11:10 +01:00
  • 27350a3465 Fix Paul Holden 2023-07-29 09:02:02 +01:00
  • 8512acf6b0 Fix PIF memory SH and SB. Paul Holden 2023-07-29 08:59:11 +01:00
  • e1b6cd4117 Remove pif prefix. Paul Holden 2023-07-28 10:48:44 +01:00
  • eed48fa5a7 Set the global bit consistently between pfne/o when setting the TLB entry. Paul Holden 2023-07-28 10:30:06 +01:00
  • 12b1222222 Tidy code for raising TLB and AdEl exceptions. Paul Holden 2023-07-28 10:17:31 +01:00
  • 352944f503 Implement entryHi as a 64 bit register. Paul Holden 2023-07-28 09:32:17 +01:00
  • 83d63b5ee6 vpn2mask doesn't need to be stored. Paul Holden 2023-07-27 22:47:37 +01:00
  • 3a848428ac Init TLBEntry fields in the constructor. Paul Holden 2023-07-27 22:38:11 +01:00
  • 2ae238c169 Get rid of mask2 and compute it directly. Paul Holden 2023-07-27 22:34:42 +01:00
  • fcd88bd6a2 Raise a TLB Mod exception if the dirty bit is clear. Paul Holden 2023-07-27 22:30:41 +01:00
  • 38f3be2ce4 Perform LW load even if the result isn't stored to trigger any exceptions. Paul Holden 2023-07-27 22:26:52 +01:00
  • 7b2ff33ff3 Add an explicit pageMaskLowBits constant. Paul Holden 2023-07-27 22:15:36 +01:00
  • 3395c6102c Fix dynarec for cop1 instructions - these can raise exceptions. Paul Holden 2023-07-27 12:24:16 +01:00
  • 24b0bed57d Remove raiseX helpers and just use raiseException. Paul Holden 2023-07-27 12:20:27 +01:00
  • d29e63dfa6 Add address helpers for dynarec. Paul Holden 2023-07-27 12:00:26 +01:00
  • f6531c00f6 Expose some cop1 functions for dynarec. Paul Holden 2023-07-27 11:58:17 +01:00
  • ce8ced1e4a Remove accessors for high parts of registers (unused now). Paul Holden 2023-07-27 11:02:54 +01:00
  • ea29a19162 Display registers using bigints. Paul Holden 2023-07-27 11:02:10 +01:00
  • 2b8091e488 Add helpers to compute reg[base]+offset. Paul Holden 2023-07-27 10:59:22 +01:00
  • 300e985252 Move memory access helpers out to a separate module. Paul Holden 2023-07-27 10:39:30 +01:00
  • e01d55c75f Always pass unsigned values to the 'slow' helpers. Paul Holden 2023-07-27 10:18:59 +01:00
  • 9b0e10ed09 Add 'fast' suffix to fast access routines. Paul Holden 2023-07-27 09:12:10 +01:00
  • 1a3f4b09cb Rename MemoryRegion functions to get/set. Paul Holden 2023-07-27 09:01:02 +01:00
  • 12f2fbaa1b Split logging functionality out into a separate class. Paul Holden 2023-07-26 23:57:29 +01:00
  • 16c2a43ba4 Use the Device implementation of readU64 and write64. Paul Holden 2023-07-26 23:44:46 +01:00
  • 0c276c731c Provide separate functions for calculating the EA for reads and writes. Paul Holden 2023-07-26 23:42:40 +01:00
  • ba2d4a70c2 Simplify MappedMemDevice accessors. Paul Holden 2023-07-26 23:03:31 +01:00
  • f2351ce7e1 Call setBigUint64 directly from store64. Paul Holden 2023-07-26 18:08:18 +01:00
  • c5518eb4a6 Remove an old/invalid FIXME. Paul Holden 2023-07-26 18:07:25 +01:00
  • 9e381a8ac8 Implement store32masked in the Device and add a store64masked. Paul Holden 2023-07-26 18:06:37 +01:00
  • 0e58b3261c Add some more helpers to MemoryRegion. Paul Holden 2023-07-26 17:53:49 +01:00
  • f8119e7774 Implement loadU64 similarly to other functions. Paul Holden 2023-07-26 16:18:58 +01:00
  • e51a3c5be5 Add some notes. Paul Holden 2023-07-26 13:38:52 +01:00
  • 1c7f4b78f1 Consolidate all the memory accessors in r4300.js. Paul Holden 2023-07-26 11:02:06 +01:00
  • 65b6876c06 Tidy presentBackBuffer. Paul Holden 2023-07-26 09:30:42 +01:00
  • 9228e60293 Push alignment further down memory handling callstack. Paul Holden 2023-07-25 22:57:05 +01:00
  • 3946907172 Implement LWL, LWR, LDL, LDR, SWL, SWL, SDL, SDR using masked writes. Paul Holden 2023-07-25 19:23:32 +01:00
  • ea4b921941 Use gprU32 for setRegU32Extend. Paul Holden 2023-07-25 19:08:27 +01:00
  • a0e5c8f09c Handle KSSEG and KSEG3 ranges. Paul Holden 2023-07-25 15:17:28 +01:00
  • 63a3a41e1b Handle status register similar to other control registers. Paul Holden 2023-07-25 15:11:18 +01:00
  • 6888fe7ee7 Fix SRAM. Paul Holden 2023-07-25 11:34:02 +01:00
  • f36781a4bf Ignore the branch delay when executing a TLB exception. Paul Holden 2023-07-24 20:47:50 +01:00
  • b33d0956e9 Fix random reg behaviour when wired >= 32. Paul Holden 2023-07-24 16:33:13 +01:00
  • 1d97a3359d Improve pagemask handling. Paul Holden 2023-07-24 16:01:29 +01:00
  • 4872aeef9b Set XContext for TLB exceptions and clear CE bits. Paul Holden 2023-07-24 14:54:36 +01:00
  • 3d33d88b49 Set XContext for TLB exceptions and clear CE bits. Paul Holden 2023-07-24 13:39:02 +01:00
  • 0ad8d742ff Implement AdEl xcontext using 64 bits. Paul Holden 2023-07-23 23:57:11 +01:00
  • 86eeefc569 EPC should be sign extended. Paul Holden 2023-07-23 23:56:28 +01:00
  • f7f7afe480 Fix config register masking. Paul Holden 2023-07-23 23:23:46 +01:00
  • d40a65d16b Fix EntryHi mask. Paul Holden 2023-07-23 23:02:15 +01:00
  • fee1794eb6 Implement DMTC0 and DMFC0 using 64 bits. Paul Holden 2023-07-23 22:58:44 +01:00
  • 8dfe9ffcf5 Make the control registers 64 bit. Paul Holden 2023-07-23 22:37:35 +01:00
  • 1c777dbad9 Rename control register members. Paul Holden 2023-07-23 22:31:32 +01:00
  • 46f0a3dfb6 Update some generated code to use control reg accessors. Paul Holden 2023-07-23 22:31:12 +01:00
  • 52b39e94f3 Tidy setTLB - no need to pass 'this' as an argument. Paul Holden 2023-07-23 22:30:39 +01:00
  • 74bc9b5aea Use accessor for incrementing count. Paul Holden 2023-07-23 22:25:53 +01:00
  • 558cd8846d Accessors for control registers. Paul Holden 2023-07-23 22:23:48 +01:00
  • 3a8b2e4d5f Split out a moveToControl helper and call from MTC0 and DMTC0. Paul Holden 2023-07-23 14:26:06 +01:00
  • fd84dad777 Tidy Paul Holden 2023-07-23 14:23:29 +01:00
  • c89f6e7490 Mask writes to EntryHi. Paul Holden 2023-07-23 14:20:30 +01:00
  • 727e295f02 Use nextpc+4 as the link address rather than pc+8. Paul Holden 2023-07-23 08:27:57 +01:00
  • 1b0af408fc Keep track of the nextPC in FragmentContext. Paul Holden 2023-07-23 08:19:42 +01:00
  • 12438a3cad Simplify how nextPC is set. Paul Holden 2023-07-23 07:58:25 +01:00
  • 38ffa3594a Ignore a local notes file I don't want to check in. Paul Holden 2023-07-23 07:52:21 +01:00
  • 3921b017e2 Implement cart write behaviour. Paul Holden 2023-07-22 22:28:46 +01:00
  • 7c4421f6df Implement broken LH/LB cart reads. Paul Holden 2023-07-22 21:49:51 +01:00
  • 97f8224fde Throw AdEl exception on misaligned instruction fetch. Paul Holden 2023-07-22 17:49:08 +01:00
  • 38bd9190ca Ensure pc is treated as a signed value so the fastpath works. Paul Holden 2023-07-22 17:47:37 +01:00
  • c0d23c0965 Implement CachedMemDevice using DataView. Paul Holden 2023-07-22 17:46:39 +01:00
  • f4e76c2ce2 Reimplement memory access to use dataviews. Paul Holden 2023-07-22 17:19:23 +01:00
  • ff9e84079c Get the DataView from the MemoryRegion. Paul Holden 2023-07-22 08:39:43 +01:00