Commit graph

1886 commits

Author SHA1 Message Date
Paul Holden
b170ee3e52 Add disassembly for DMFC0 and DMTC0. 2023-07-12 23:09:35 +01:00
Paul Holden
fee925cd8d Rename controlSR to controlStatus. 2023-07-12 23:06:42 +01:00
Paul Holden
f50aaea149 Remove logging for read-only control registers. 2023-07-12 23:03:42 +01:00
Paul Holden
c43f16f8e1 Stop logging context register writes. 2023-07-12 23:00:58 +01:00
Paul Holden
3a075ae1de Partially implement XContext masking. 2023-07-12 22:58:56 +01:00
Paul Holden
922856354f Mask writes to the wired register. 2023-07-12 22:51:51 +01:00
Paul Holden
f71ccae831 Mask out the writable bits of the context register. 2023-07-12 22:45:07 +01:00
Paul Holden
1ea5d0bf79 Add placeholder implementations for DMTC0 and DMTC0 2023-07-12 22:37:22 +01:00
Paul Holden
56c37d2984 Fix MTC0/MFC0 for invalid registers.
Reads from invalid control registers will use the value last written to any control register.
2023-07-12 22:25:36 +01:00
Paul Holden
e7e6ae1aa4 Ignore SYNC (is a nop on Vr4300). 2023-07-12 22:18:10 +01:00
Paul Holden
d13960cbd6 Remove generateShiftVariable and just inline directly. 2023-07-12 22:16:22 +01:00
Paul Holden
4bd883b425 Fix SRAV.
Just like SRA this seems to shift the entire 64 bit reg, trunc to 32 bits, then sign extend.
2023-07-12 22:14:12 +01:00
Paul Holden
628e58cf21 Explicitly generate SLL. 2023-07-12 22:06:32 +01:00
Paul Holden
fe92c9b6e4 Explicitly generate SRL. 2023-07-12 22:05:53 +01:00
Paul Holden
e4e0f5bb40 Fix SRA.
This reads all 64 bits, shifts, then sign extends the 32 bit result.
2023-07-12 20:12:07 +01:00
Paul Holden
2934c0750f Fix missing closing paren in CVT.S.L. 2023-07-12 19:55:28 +01:00
Paul Holden
9cfaa4db7c Template string. 2023-07-12 19:39:18 +01:00
Paul Holden
a35912cba3 Fix DSLLV, DSRLV, DSRAV with zero shifts.
JS does not like 32 bit shifts.
2023-07-12 13:45:09 +01:00
Paul Holden
5af1fe4d00 Add some missing cop0 control reg names. 2023-07-12 13:33:08 +01:00
Paul Holden
b7ddfe1fc9 Implement LL, LLD, SC, SCD. 2023-07-12 09:00:51 +01:00
Paul Holden
ef28af573e Fix DDIVU (mixing BigInt and Number). 2023-07-11 23:57:58 +01:00
Paul Holden
3296e65eb4 Fix DSRL. 2023-07-11 23:29:37 +01:00
Paul Holden
206f1e2928 Fix DSRA. 2023-07-11 23:27:50 +01:00
Paul Holden
a791225f13 Fix DSLL32.
This was clobbering the register before reading from it.
2023-07-11 23:24:31 +01:00
Paul Holden
54206815c4 Fix DSUB (undefined helper). 2023-07-11 23:21:05 +01:00
Paul Holden
f7b99215e3 Fix DSLL for shift of 32.
JS treats >>>32 as >>> 0.
2023-07-11 23:20:43 +01:00
Paul Holden
b2ec2d4873 Include address and value in failed rom accesses. 2023-07-10 23:28:05 +01:00
Paul Holden
272097b19a Tidy LWL, LWR, SWL, SWR. 2023-07-10 23:24:04 +01:00
Paul Holden
824bbba928 Print md5 on boot. 2023-07-10 23:05:11 +01:00
Paul Holden
592cfb22c8 Add TODO for LDL/SDR. 2023-07-10 23:03:46 +01:00
Paul Holden
e82fd7afd4 Add save type for 56a48bb9af762b5b. 2023-07-10 23:03:27 +01:00
Paul Holden
4d02645a3f Add LDL, LDR, SDL, SDR. 2023-07-10 23:03:09 +01:00
Paul Holden
663dfed48b Add toString64_bigint. 2023-07-10 23:01:27 +01:00
Paul Holden
b921414899 Add MD5 support, based on https://github.com/blueimp/JavaScript-MD5.
I've modified this to take ArrayBuffers rather than raw strings, which avoids a lot of character encoding pain.
2023-07-08 09:37:35 +01:00
Paul Holden
c487299b70 Implement missing CVT instructions. 2023-07-07 20:58:33 +01:00
Paul Holden
45b3c24381 Implement full width mode. 2023-07-07 20:48:57 +01:00
Paul Holden
1f714d397f Fix DDIV and DDIVU.
These now pass https://github.com/PeterLemon/N64/tree/master/CPUTest/CPU/DDIV and https://github.com/PeterLemon/N64/tree/master/CPUTest/CPU/DDIVU.
2023-07-07 09:33:57 +01:00
Paul Holden
0fe2ae5e29 Fix DIV and DIVU.
These now pass https://github.com/PeterLemon/N64/tree/master/CPUTest/CPU/DIV and https://github.com/PeterLemon/N64/tree/master/CPUTest/CPU/DIVU.
2023-07-07 09:16:32 +01:00
Paul Holden
9ccbff688d Fix DMULT and DMULTU.
Now passes https://github.com/PeterLemon/N64/tree/master/CPUTest/CPU/DMULTU.
2023-07-07 08:27:25 +01:00
Paul Holden
f64d931003 Ensure executeCop1 instruction is synced on boot. 2023-07-07 08:25:48 +01:00
Paul Holden
3ae5c9a291 Handle reads from 0xa5000508.
This gets F-Zero as far as the first splash screen. Still hangs though.
2023-07-06 22:14:39 +01:00
Paul Holden
2f794221e5 Handle memory access outside of rdram range. 2023-07-06 22:13:21 +01:00
Paul Holden
25a81c52c9 PI fixes:
* Implement reg reads.
* Implement PI_STATUS_INTERRUPT.
* Handle weirdness with short (<128 byte) transfers.
* Update address registers after the transfer.
2023-07-06 21:34:54 +01:00
Paul Holden
b88cf3a377 Improve error message - this isn't necessarily a read. 2023-07-05 23:12:55 +01:00
Paul Holden
df8beb140f Print values in checkCauseIP3Consistent. 2023-07-05 23:03:28 +01:00
Paul Holden
e909c6cf9e Add basic SRAM support. 2023-07-05 23:03:09 +01:00
Paul Holden
85e56de0cd Template strings. 2023-07-05 00:07:25 +01:00
Paul Holden
d90150c2b7 Init ucode_table for more microcodes. 2023-07-05 00:04:37 +01:00
Paul Holden
3c9bcbbfd1 Implement executeSetRDPOtherMode.
This allows Zelda OOT to render the intro logo.
2023-07-05 00:04:09 +01:00
Paul Holden
00f9592c42 Width>0x300 hack does seem to be needed.
Without this, Spiderman renders too small.
2023-07-04 23:41:25 +01:00