Paul Holden
|
8481a04545
|
Use a DataView rather than bittwiddling.
https://www.measurethat.net/Benchmarks/Show/26379/
|
2023-07-22 08:25:44 +01:00 |
|
Paul Holden
|
05f9d47c27
|
Don't format values if they're not logged.
|
2023-07-22 08:22:55 +01:00 |
|
Paul Holden
|
eee8f2d13c
|
Fix PIRamDevice readU8.
|
2023-07-22 08:13:03 +01:00 |
|
Paul Holden
|
45bfaaea41
|
SPMem is accessible from 0xa4000000 to 0xa4040000, but wraps every 0x2000 bytes.
|
2023-07-22 08:12:25 +01:00 |
|
Paul Holden
|
9443bb32af
|
Tidy
|
2023-07-22 07:23:13 +01:00 |
|
Paul Holden
|
245a811088
|
Implement LLD using setRegU64.
|
2023-07-21 15:34:43 +01:00 |
|
Paul Holden
|
9f74b540e3
|
Implement generateOR and generateNOR using 64 bit instructions.
|
2023-07-21 15:31:27 +01:00 |
|
Paul Holden
|
b5d9f2fcd5
|
Implement MFHI, MFLO, MTHI, MTLO using 64 bit moves.
|
2023-07-21 15:26:02 +01:00 |
|
Paul Holden
|
d10a7ca8e0
|
Rename sourceBits etc to sBits.
|
2023-07-21 15:07:10 +01:00 |
|
Paul Holden
|
4a81400fee
|
Reorder methods.
|
2023-07-21 15:04:38 +01:00 |
|
Paul Holden
|
ec5fc5b14c
|
Tidy cpu1 64 bit reg handling.
* rename _i64_bigint to S64/U64.
* load bigints directly
|
2023-07-21 15:02:57 +01:00 |
|
Paul Holden
|
d51a3d7206
|
Rename store_i64_bigint to storeU64.
|
2023-07-21 14:43:03 +01:00 |
|
Paul Holden
|
73247185b4
|
Rename load_i32, load_f32, load_f64. Remove load_i64_number.
|
2023-07-21 14:42:02 +01:00 |
|
Paul Holden
|
d19e42944c
|
Rename store_f32 and store_f64.
|
2023-07-21 14:37:16 +01:00 |
|
Paul Holden
|
4fc4bc65bd
|
store_64_hi_lo is unused.
|
2023-07-21 14:35:17 +01:00 |
|
Paul Holden
|
4647da07cd
|
Implement store_i64_bigint by directly writing to BigUint64Array.
|
2023-07-21 14:34:42 +01:00 |
|
Paul Holden
|
39aece1e73
|
Implement LD and LDC1 using load_u64_bigint.
|
2023-07-21 14:31:02 +01:00 |
|
Paul Holden
|
36748af5ce
|
Fix cpu1 regnames.
|
2023-07-21 14:30:00 +01:00 |
|
Paul Holden
|
3f16235a04
|
Remove store_i64_number (unused).
|
2023-07-21 14:22:35 +01:00 |
|
Paul Holden
|
b0ed4761ab
|
Rename store_i32 to storeS32.
|
2023-07-21 14:21:33 +01:00 |
|
Paul Holden
|
8fe816b5b2
|
Add regS64 and regU64. Zero the entire register.
|
2023-07-21 14:19:21 +01:00 |
|
Paul Holden
|
d14e3dc5b1
|
Rename CPU1 registers.
|
2023-07-21 14:17:33 +01:00 |
|
Paul Holden
|
176e2d2218
|
Implement branches using BigInt.
|
2023-07-21 13:30:28 +01:00 |
|
Paul Holden
|
6d64a113b1
|
Use camelCase for naming locals.
|
2023-07-21 13:09:14 +01:00 |
|
Paul Holden
|
3ebfab7c89
|
Tidy SDC1.
|
2023-07-21 13:07:33 +01:00 |
|
Paul Holden
|
7ca5a10951
|
Use BigIntArray to store results from DIV, DIVU, DDIV, DDIVU.
|
2023-07-21 13:03:30 +01:00 |
|
Paul Holden
|
c8ad802272
|
Store DMULT/DMULTU results using BigIntArray.
|
2023-07-21 12:56:08 +01:00 |
|
Paul Holden
|
f931df95a1
|
Add BigInt64Arrays for multlo/multhi and write results from MULT and MULTU without shifts.
|
2023-07-21 12:50:06 +01:00 |
|
Paul Holden
|
b5ebd0ca51
|
Rename multHi/multLo for consistency with other naming.
|
2023-07-21 07:30:16 +01:00 |
|
Paul Holden
|
26af33f2e8
|
Implement SLT using BigInt.
|
2023-07-21 07:14:28 +01:00 |
|
Paul Holden
|
00ca18fbc5
|
Implement SLTIU using BigInt.
|
2023-07-21 07:11:16 +01:00 |
|
Paul Holden
|
00cb37323a
|
Implement XORI using BigInt.
|
2023-07-20 14:59:47 +01:00 |
|
Paul Holden
|
9ab66694d0
|
Implement ANDI using BigInt.
|
2023-07-20 14:59:25 +01:00 |
|
Paul Holden
|
8d2b6ac468
|
Implement ORI using BigInt.
I don't think the s==t optimisation is worth the extra complexity.
|
2023-07-20 14:45:49 +01:00 |
|
Paul Holden
|
169cf1e9c5
|
Implement AND, OR, XOR, NOR using BigInt.
It's simpler and benchmarks show this is faster: https://www.measurethat.net/Benchmarks/Show/26326/0/and-for-vr4300
|
2023-07-20 14:41:38 +01:00 |
|
Paul Holden
|
26ce8f08b7
|
Rename setGPR_s64_lo_hi to setRegS64LoHi.
|
2023-07-20 14:35:33 +01:00 |
|
Paul Holden
|
99563e6063
|
Rename setGPR_s32_lo to setRegS32Lo.
|
2023-07-20 14:34:16 +01:00 |
|
Paul Holden
|
d5082e25cc
|
Rename setGPR_s32_signed to setRegS32Extend.
|
2023-07-20 14:33:10 +01:00 |
|
Paul Holden
|
f6299a916d
|
Rename setGPR_s32_unsigned to setRegU32Extend.
|
2023-07-20 14:28:22 +01:00 |
|
Paul Holden
|
8e87f1c55b
|
Tidy
|
2023-07-20 14:25:53 +01:00 |
|
Paul Holden
|
22a1560eab
|
Rename genSrcRegHi to genSrcRegS32Hi.
|
2023-07-20 14:23:55 +01:00 |
|
Paul Holden
|
aa0f8961e5
|
Rename genSrcRegLo to genSrcRegS32Lo.
|
2023-07-20 14:22:34 +01:00 |
|
Paul Holden
|
296148c6db
|
Rename getGPR_s32_signed to getRegS32Lo.
|
2023-07-20 14:21:10 +01:00 |
|
Paul Holden
|
f4b63829d3
|
Rename getGPR_s32_unsigned to getRegU32Lo.
|
2023-07-20 14:18:37 +01:00 |
|
Paul Holden
|
f4dbb62c61
|
Log bad pagemasks rather than halting.
|
2023-07-20 14:13:31 +01:00 |
|
Paul Holden
|
06dbcff845
|
Rename getGPR_s32_hi_signed to getRegS32Hi.
|
2023-07-20 14:12:01 +01:00 |
|
Paul Holden
|
c84f1dc77b
|
Rename getGPR_s32_hi_unsigned to getRegU32Hi.
|
2023-07-20 14:09:34 +01:00 |
|
Paul Holden
|
606d9c9a40
|
Rename setGPR_s64_bigint to setRegU64.
|
2023-07-20 14:06:57 +01:00 |
|
Paul Holden
|
d3a3f8e7df
|
Tidy
|
2023-07-20 14:04:06 +01:00 |
|
Paul Holden
|
42f9a73e89
|
Rename getGPR_u64_bigint to getRegU64.
|
2023-07-20 14:03:50 +01:00 |
|