mirror of
https://github.com/Dillonb/n64.git
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250 lines
7.1 KiB
C
250 lines
7.1 KiB
C
#ifndef N64_MIPS_INSTRUCTIONS_H
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#define N64_MIPS_INSTRUCTIONS_H
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#include "r4300i.h"
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#include "mips_instruction_decode.h"
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#define check_signed_overflow_add(op1, op2, res) (((~((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
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#define check_signed_overflow_sub(op1, op2, res) (((((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
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#define check_address_error(mask, virtual) (((!N64CP0.is_64bit_addressing) && (s32)(virtual) != (virtual)) || (((virtual) & (mask)) != 0))
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#define MIPS_INSTR(NAME) void NAME(mips_instruction_t instruction)
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// https://stackoverflow.com/questions/25095741/how-can-i-multiply-64-bit-operands-and-get-128-bit-result-portably/58381061#58381061
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/* Prevents a partial vectorization from GCC. */
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#if defined(__GNUC__) && !defined(__clang__) && defined(__i386__)
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__attribute__((__target__("no-sse")))
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#endif
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INLINE u64 multu_64_to_128(u64 lhs, u64 rhs, u64 *high) {
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/*
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* GCC and Clang usually provide __uint128_t on 64-bit targets,
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* although Clang also defines it on WASM despite having to use
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* builtins for most purposes - including multiplication.
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*/
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#if defined(__SIZEOF_INT128__) && !defined(__wasm__)
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__uint128_t product = (__uint128_t)lhs * (__uint128_t)rhs;
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*high = (u64)(product >> 64);
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return (u64)(product & 0xFFFFFFFFFFFFFFFF);
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/* Use the _umul128 intrinsic on MSVC x64 to hint for mulq. */
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#elif defined(_MSC_VER) && defined(_M_IX64)
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# pragma intrinsic(_umul128)
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/* This intentionally has the same signature. */
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return _umul128(lhs, rhs, high);
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#else
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/*
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* Fast yet simple grade school multiply that avoids
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* 64-bit carries with the properties of multiplying by 11
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* and takes advantage of UMAAL on ARMv6 to only need 4
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* calculations.
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*/
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/* First calculate all of the cross products. */
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uint64_t lo_lo = (lhs & 0xFFFFFFFF) * (rhs & 0xFFFFFFFF);
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uint64_t hi_lo = (lhs >> 32) * (rhs & 0xFFFFFFFF);
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uint64_t lo_hi = (lhs & 0xFFFFFFFF) * (rhs >> 32);
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uint64_t hi_hi = (lhs >> 32) * (rhs >> 32);
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/* Now add the products together. These will never overflow. */
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uint64_t cross = (lo_lo >> 32) + (hi_lo & 0xFFFFFFFF) + lo_hi;
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uint64_t upper = (hi_lo >> 32) + (cross >> 32) + hi_hi;
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*high = upper;
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return (cross << 32) | (lo_lo & 0xFFFFFFFF);
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#endif /* portable */
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}
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/* Prevents a partial vectorization from GCC. */
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#if defined(__GNUC__) && !defined(__clang__) && defined(__i386__)
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__attribute__((__target__("no-sse")))
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#endif
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INLINE u64 mult_64_to_128(s64 lhs, s64 rhs, u64 *high) {
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/*
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* GCC and Clang usually provide __uint128_t on 64-bit targets,
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* although Clang also defines it on WASM despite having to use
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* builtins for most purposes - including multiplication.
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*/
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#if defined(__SIZEOF_INT128__) && !defined(__wasm__)
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__int128_t product = (__int128_t)lhs * (__int128_t)rhs;
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*high = (s64)(product >> 64);
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return (s64)(product & 0xFFFFFFFFFFFFFFFF);
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/* Use the _mul128 intrinsic on MSVC x64 to hint for mulq. */
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#elif defined(_MSC_VER) && defined(_M_IX64)
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# pragma intrinsic(_mul128)
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/* This intentionally has the same signature. */
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return _mul128(lhs, rhs, high);
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#else
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/*
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* Fast yet simple grade school multiply that avoids
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* 64-bit carries with the properties of multiplying by 11
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* and takes advantage of UMAAL on ARMv6 to only need 4
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* calculations.
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*/
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logfatal("This code will be broken for signed multiplies!");
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/* First calculate all of the cross products. */
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uint64_t lo_lo = (lhs & 0xFFFFFFFF) * (rhs & 0xFFFFFFFF);
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uint64_t hi_lo = (lhs >> 32) * (rhs & 0xFFFFFFFF);
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uint64_t lo_hi = (lhs & 0xFFFFFFFF) * (rhs >> 32);
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uint64_t hi_hi = (lhs >> 32) * (rhs >> 32);
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/* Now add the products together. These will never overflow. */
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uint64_t cross = (lo_lo >> 32) + (hi_lo & 0xFFFFFFFF) + lo_hi;
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uint64_t upper = (hi_lo >> 32) + (cross >> 32) + hi_hi;
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*high = upper;
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return (cross << 32) | (lo_lo & 0xFFFFFFFF);
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#endif /* portable */
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}
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MIPS_INSTR(mips_nop);
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MIPS_INSTR(mips_addi);
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MIPS_INSTR(mips_addiu);
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MIPS_INSTR(mips_daddi);
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MIPS_INSTR(mips_andi);
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MIPS_INSTR(mips_blez);
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MIPS_INSTR(mips_blezl);
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MIPS_INSTR(mips_beq);
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MIPS_INSTR(mips_beql);
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MIPS_INSTR(mips_bgtz);
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MIPS_INSTR(mips_bgtzl);
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MIPS_INSTR(mips_bne);
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MIPS_INSTR(mips_bnel);
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MIPS_INSTR(mips_cache);
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MIPS_INSTR(mips_j);
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MIPS_INSTR(mips_jal);
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MIPS_INSTR(mips_slti);
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MIPS_INSTR(mips_sltiu);
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MIPS_INSTR(mips_mfc0);
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MIPS_INSTR(mips_mtc0);
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MIPS_INSTR(mips_dmfc0);
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MIPS_INSTR(mips_dmtc0);
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MIPS_INSTR(mips_eret);
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MIPS_INSTR(mips_ld);
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MIPS_INSTR(mips_lui);
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MIPS_INSTR(mips_lbu);
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MIPS_INSTR(mips_lhu);
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MIPS_INSTR(mips_lh);
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MIPS_INSTR(mips_lw);
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MIPS_INSTR(mips_lwu);
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MIPS_INSTR(mips_sb);
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MIPS_INSTR(mips_sh);
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MIPS_INSTR(mips_sd);
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MIPS_INSTR(mips_sw);
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MIPS_INSTR(mips_ori);
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MIPS_INSTR(mips_xori);
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MIPS_INSTR(mips_daddiu);
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MIPS_INSTR(mips_lb);
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MIPS_INSTR(mips_ldc1);
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MIPS_INSTR(mips_sdc1);
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MIPS_INSTR(mips_lwc1);
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MIPS_INSTR(mips_swc1);
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MIPS_INSTR(mips_lwl);
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MIPS_INSTR(mips_lwr);
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MIPS_INSTR(mips_swl);
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MIPS_INSTR(mips_swr);
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MIPS_INSTR(mips_ldl);
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MIPS_INSTR(mips_ldr);
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MIPS_INSTR(mips_sdl);
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MIPS_INSTR(mips_sdr);
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MIPS_INSTR(mips_ll);
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MIPS_INSTR(mips_lld);
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MIPS_INSTR(mips_sc);
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MIPS_INSTR(mips_scd);
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MIPS_INSTR(mips_spc_sll);
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MIPS_INSTR(mips_spc_srl);
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MIPS_INSTR(mips_spc_sra);
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MIPS_INSTR(mips_spc_srav);
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MIPS_INSTR(mips_spc_sllv);
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MIPS_INSTR(mips_spc_srlv);
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MIPS_INSTR(mips_spc_jr);
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MIPS_INSTR(mips_spc_jalr);
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MIPS_INSTR(mips_spc_syscall);
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MIPS_INSTR(mips_spc_mfhi);
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MIPS_INSTR(mips_spc_mthi);
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MIPS_INSTR(mips_spc_mflo);
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MIPS_INSTR(mips_spc_mtlo);
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MIPS_INSTR(mips_spc_dsllv);
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MIPS_INSTR(mips_spc_dsrlv);
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MIPS_INSTR(mips_spc_dsrav);
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MIPS_INSTR(mips_spc_mult);
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MIPS_INSTR(mips_spc_multu);
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MIPS_INSTR(mips_spc_div);
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MIPS_INSTR(mips_spc_divu);
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MIPS_INSTR(mips_spc_dmult);
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MIPS_INSTR(mips_spc_dmultu);
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MIPS_INSTR(mips_spc_ddiv);
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MIPS_INSTR(mips_spc_ddivu);
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MIPS_INSTR(mips_spc_add);
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MIPS_INSTR(mips_spc_addu);
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MIPS_INSTR(mips_spc_nor);
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MIPS_INSTR(mips_spc_and);
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MIPS_INSTR(mips_spc_sub);
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MIPS_INSTR(mips_spc_subu);
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MIPS_INSTR(mips_spc_or);
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MIPS_INSTR(mips_spc_xor);
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MIPS_INSTR(mips_spc_slt);
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MIPS_INSTR(mips_spc_sltu);
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MIPS_INSTR(mips_spc_dadd);
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MIPS_INSTR(mips_spc_daddu);
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MIPS_INSTR(mips_spc_dsub);
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MIPS_INSTR(mips_spc_dsubu);
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MIPS_INSTR(mips_spc_teq);
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MIPS_INSTR(mips_spc_break);
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MIPS_INSTR(mips_spc_tne);
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MIPS_INSTR(mips_spc_dsll);
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MIPS_INSTR(mips_spc_dsrl);
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MIPS_INSTR(mips_spc_dsra);
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MIPS_INSTR(mips_spc_dsll32);
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MIPS_INSTR(mips_spc_dsrl32);
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MIPS_INSTR(mips_spc_dsra32);
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MIPS_INSTR(mips_spc_tge);
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MIPS_INSTR(mips_spc_tgeu);
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MIPS_INSTR(mips_spc_tlt);
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MIPS_INSTR(mips_spc_tltu);
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MIPS_INSTR(mips_ri_bltz);
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MIPS_INSTR(mips_ri_bltzl);
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MIPS_INSTR(mips_ri_bgez);
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MIPS_INSTR(mips_ri_bgezl);
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MIPS_INSTR(mips_ri_bltzal);
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MIPS_INSTR(mips_ri_bgezal);
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MIPS_INSTR(mips_ri_bgezall);
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MIPS_INSTR(mips_ri_tgei);
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MIPS_INSTR(mips_ri_tgeiu);
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MIPS_INSTR(mips_ri_tlti);
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MIPS_INSTR(mips_ri_tltiu);
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MIPS_INSTR(mips_ri_teqi);
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MIPS_INSTR(mips_ri_tnei);
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MIPS_INSTR(mips_invalid);
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MIPS_INSTR(mips_mfc2);
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MIPS_INSTR(mips_mtc2);
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MIPS_INSTR(mips_dmfc2);
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MIPS_INSTR(mips_dmtc2);
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MIPS_INSTR(mips_cfc2);
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MIPS_INSTR(mips_ctc2);
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MIPS_INSTR(mips_cp2_invalid);
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#endif //N64_MIPS_INSTRUCTIONS_H
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