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168 lines
6.5 KiB
ReStructuredText
168 lines
6.5 KiB
ReStructuredText
MIPS Interface
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==============
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0x04300000 - MI_MODE_REG (Read / Write)
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--------------------------------------
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Sets and retrieves some values. I am uncertain of what they are used for.
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More importantly, this register allows the game to lower the DP interrupt.
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Writes
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^^^^^^
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+-----+-----------------------------------------------------------+
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| Bit | Explanation |
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+=====+===========================================================+
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| 0-6 | Sets init length (??) |
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+-----+-----------------------------------------------------------+
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| 7 | Clear init mode (??) |
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+-----+-----------------------------------------------------------+
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| 8 | Set init mode (??) |
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+-----+-----------------------------------------------------------+
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| 9 | Clear ebus test mode (??) |
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+-----+-----------------------------------------------------------+
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| 10 | Set ebus test mode (??) |
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+-----+-----------------------------------------------------------+
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| 11 | Lower DP Interrupt: Sets the bit in MI_INTR_REG to low |
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+-----+-----------------------------------------------------------+
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| 12 | Clear RDRAM reg mode (??) |
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+-----+-----------------------------------------------------------+
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| 13 | Set RDRAM reg mode (??) |
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+-----+-----------------------------------------------------------+
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Writes with "set" bits high will set the bits in the actual register to high. Writes with "set" bits low will have no effect.
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Writes with "clear" bits high will clear the bits in the actual register. Writes with "clear" bits low will have no effect.
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If both the "set" and "clear" bits are high, the value is set (?? I think ??)
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Reads
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^^^^^
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+-----+-------------------------------------------------------+
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| Bit | Explanation |
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+=====+=======================================================+
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| 0-6 | Gets init length - returns the value written above |
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+-----+-------------------------------------------------------+
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| 7 | Gets init mode - returns the value written above |
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+-----+-------------------------------------------------------+
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| 8 | Gets ebus test mode - returns the value written above |
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+-----+-------------------------------------------------------+
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| 9 | Gets RDRAM reg mode - returns the value written above |
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+-----+-------------------------------------------------------+
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0x04300004 - MI_VERSION_REG (Read only)
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--------------------------------------
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+-------+--------------+
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| Bit | Explanation |
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+=======+==============+
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| 0-7 | IO Version |
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+-------+--------------+
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| 8-15 | RAC Version |
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+-------+--------------+
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| 16-23 | RDP Version |
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+-------+--------------+
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| 24-31 | RSP Version |
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+-------+--------------+
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This register should return 0x02020102 always.
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0x04300008 - MI_INTR_REG (Read only)
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-----------------------------------
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Bits in this register are raised and lowered as interrupts are raised and lowered by other parts of the system.
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+-----+----------------------------------------------------------------------------------------------------------------------------+
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| Bit | Explanation |
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+=====+============================================================================================================================+
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| 0 | SP Interrupt - Set by the RSP when requested by a write to the SP status register, and optionally when the RSP halts. |
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+-----+----------------------------------------------------------------------------------------------------------------------------+
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| 1 | SI Interrupt - Set by the serial interface, when SI DMAs to/from PIF RAM finish. |
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+-----+----------------------------------------------------------------------------------------------------------------------------+
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| 2 | AI Interrupt - Set by the audio interface, when there are no more samples remaining in an audio stream |
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+-----+----------------------------------------------------------------------------------------------------------------------------+
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| 3 | VI Interrupt - Set by the video interface, when V_CURRENT == V_INTR. Allows an interrupt to be raised on a given scanline. |
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+-----+----------------------------------------------------------------------------------------------------------------------------+
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| 4 | PI Interrupt - Set by the peripheral interface, when a PI DMA between the cartridge and RDRAM finishes. |
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+-----+----------------------------------------------------------------------------------------------------------------------------+
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| 5 | DP Interrupt - Set by the RDP, when a full sync completes. |
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+-----+----------------------------------------------------------------------------------------------------------------------------+
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0x0430000C - MI_INTR_MASK_REG (Read / Write)
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-------------------------------------------
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This register sets up a mask. If (MI_INTR_REG & MI_INTR_MASK_REG) != 0, then a MIPS interrupt is raised.
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Writes
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^^^^^^
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+-----+---------------+
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| Bit | Explanation |
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+=====+===============+
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| 0 | Clear SP Mask |
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+-----+---------------+
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| 1 | Set SP Mask |
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+-----+---------------+
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| 2 | Clear SI Mask |
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+-----+---------------+
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| 3 | Set SI Mask |
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+-----+---------------+
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| 4 | Clear AI Mask |
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+-----+---------------+
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| 5 | Set AI Mask |
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+-----+---------------+
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| 6 | Clear VI Mask |
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+-----+---------------+
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| 7 | Set VI Mask |
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+-----+---------------+
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| 8 | Clear PI Mask |
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+-----+---------------+
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| 9 | Set PI Mask |
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+-----+---------------+
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| 10 | Clear DP Mask |
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+-----+---------------+
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| 11 | Set DP Mask |
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+-----+---------------+
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See MI_MODE_REG for an explanation on set/clear bits.
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Reads
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^^^^^
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+-----+---------------+
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| Bit | Explanation |
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+=====+===============+
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| 0 | SP Mask |
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+-----+---------------+
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| 1 | SI Mask |
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+-----+---------------+
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| 2 | AI Mask |
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+-----+---------------+
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| 3 | VI Mask |
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+-----+---------------+
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| 4 | PI Mask |
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+-----+---------------+
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| 5 | DP Mask |
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+-----+---------------+
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Video Interface
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===============
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TODO
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Audio Interface
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===============
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TODO
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Peripheral Interface
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====================
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TODO
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RDRAM Interface
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===============
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TODO
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Serial Interface
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================
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TODO
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