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18 lines
No EOL
601 B
NASM
18 lines
No EOL
601 B
NASM
arch n64.cpu
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endian msb
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include "regs.inc"
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origin $00000000
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base $80000000
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//; These lines should be run with the interpreter, so the values of t0 and t1 are predictable
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addiu t0, r0, 0
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addiu t1, r0, 1
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//; The rest should be run with the dynarec.
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//; This sets up this register so it can't be eliminated with constant propagation first usage is here,
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//; and the last usage is in the delay slot that should be skipped.
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//; This way we can test that the registers are getting flushed correctly, and the delay slot is getting skipped correctly.
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addiu t0, t0, 1
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bnel t0, t1, 0x80000020
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addiu t0, t0, 1 |