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64 lines
4.5 KiB
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64 lines
4.5 KiB
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Overview
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========
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The Nintendo 64 is an early 3D console with some interesting quirks. Let's get right into it.
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The system is often thought of as having two main components - the CPU, and the Reality Coprocessor (RCP), with the RCP again being divided into two components, the Reality Signal Processor (RSP) and the Reality Display Processor (RDP.)
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The system has 4MiB of RDRAM, expandable with an add-on (Expansion Pak) to 8MiB. The system is designed in such a way that all 3 processors (CPU, RSP, RDP) can access the same memory. Thus, this RAM acts as both normal system RAM and VRAM at the same time.
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Interestingly, each byte in RDRAM is actually 9 bits. In other computer systems with RDRAM, this 9th bit is normally used as a parity bit for data integrity checking, but it has been repurposed in the N64 as extra storage for the RDP. The RDP uses it for depth buffering and anti-aliasing, usually.
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The 9th bits are usually implemented in emulators as an entirely separate structure from the main RDRAM array.
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All memory is accessed using big-endian.
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CPU Overview
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------------
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The CPU is a fairly standard 64 bit MIPS r4300i chip.
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It has 32 *64-bit* registers. The first register, r0 or $zero, is hardwired to a value of 0, at all times. There are also special-purpose registers for things like multiplication.
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It has a 64 bit program counter and can be configured to use 32 bit or 64 bit addresses to access memory, though in practice the vast majority of software uses 32 bit addressing. It can load and store 8, 16, 32, and 64 bit values. All memory accesses must be aligned, and loads/stores with unaligned addresses will throw exceptions.
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All memory accesses, including instruction fetches, use virtual memory. There are segments of the address space that use fixed translation, and segments that are configurable.
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MIPS has the concept of "coprocessors" built directly into the instruction set. Each one is numbered, and there are special opcodes for interacting with them, including MTCx/MFCx (move to/from coprocessor x), which are used to move data between the main CPU registers and the coprocessor's registers.
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Coprocessor zero, or COP0, is the "system control coprocessor." It is through COP0 that virtual memory is set up, exceptions and interrupts are controlled, the CPU status is accessed, among other things. There are 32 32-bit registers, most of which have special uses.
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Coprocessor one, or COP1, is a floating-point unit, or FPU. It supports a variety of floating point operations on its 32 floating-point registers.
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Reality Coprocessor Overview
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----------------------------
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As mentioned above, the RCP is actually composed of two separate components, the RSP and the RDP.
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Reality Signal Processor Overview
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The RSP is a secondary CPU mostly used for 3D and audio calculations. While it runs at 2/3rds the speed of the main CPU, it has powerful *Single Instruction Multiple Data* (SIMD) instructions that make it extremely suited for the type of math required by 3D graphics. These instructions perform the same operation on multiple values at once.
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It is effectively a stripped-down version of the MIPS chip used for the main CPU, missing some instructions and running at a slightly slower speed.
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It has 32 *32-bit* registers. Note that this is different than the main CPU, which has 64-bit registers! As in the CPU, the first register, r0 or $zero, is hardwired to 0 at all times.
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The RSP has no COP0 in the same way the CPU does. Instead, the COP0 registers are used to communicate with the DMA engine, RDP, and various other things. It also does not have a floating point unit available on COP1.
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It, however, does have a Vector Unit (VU) available as COP2. The VU has quite a few registers which are discussed in the RSP section below. Sometimes, the normal operations of this CPU are referred to as the Scalar Unit (SU) to differentiate them from the vector unit.
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All memory accesses use a physical address, there is no virtual memory involved here.
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Unlike the CPU, the RSP is capable of reading and writing unaligned values. Not only will these accesses not throw exceptions, they'll work perfectly! Again, note that memory accesses can only be to DMEM.
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SP IMEM is only 0x1000 bytes in size and the bottom 12 bits of the program counter are used to address it. Because of this, the program counter can be thought of as being a simple 12 bit value.
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Reality Display Processor Overview
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The RDP is a rasterizer used to display images on-screen.
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