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  • 6d5906487c WIP, need to figure out the swapchain Dillon Beliveau 2022-07-02 20:31:14 -07:00
  • b727285cbe Vulkan widget initializing correctly Dillon Beliveau 2022-07-02 15:29:03 -07:00
  • 6999a7ee2c Switch libgtk-3-dev dependency for libdbus-1-dev Dillon Beliveau 2022-07-02 12:12:22 -07:00
  • 0d74b56cc7 WIP Qt frontend Dillon Beliveau 2022-07-02 12:10:45 -07:00
  • 5a0c7fa257 Update UI file for gtk4 gtk-frontend-2 Dillon Beliveau 2022-07-01 18:31:54 -07:00
  • 690e176c33 Merge branch 'master' into gtk-frontend-2 Dillon Beliveau 2022-07-01 18:09:46 -07:00
  • 10a4770105 Use xdg-desktop-portal with NFD Dillon Beliveau 2022-07-01 18:08:12 -07:00
  • 2b9c51b711 build with GTK4 Dillon Beliveau 2022-07-01 18:07:45 -07:00
  • 7858e376d4 Merge branch 'master' into gtk-frontend-2 Dillon Beliveau 2022-07-01 17:56:09 -07:00
  • 13b1639557 Latest version of parallel-rdp Dillon Beliveau 2022-06-30 00:10:29 -07:00
  • 574541b563 log a nice message when an unexpected exception is seen instead of emitting int3 Dillon Beliveau 2022-06-19 12:38:56 -07:00
  • 287901bace JIT updates to support more exceptions, CPU TLB miss exceptions still not working Dillon Beliveau 2022-06-19 00:50:44 -07:00
  • 4609ffe60f Correct default COP0.Status and COP0.Config values for PIF HLE CocoSimone 2022-06-19 10:02:05 +02:00
  • 8249fd929f I guess my emulator has a name now Dillon Beliveau 2022-06-18 23:52:13 -07:00
  • d4e94fc381 Fix PI DMA outside of REGION_CART_1_2 Dillon Beliveau 2022-06-18 23:22:42 -07:00
  • 4151af79a6 Oops Dillon Beliveau 2022-06-18 16:11:57 -07:00
  • 50aab2ab9f cleanup exception handling code slightly Dillon Beliveau 2022-06-18 16:07:53 -07:00
  • fd1d1175e8 RSP fixes in VRCP/VRCPL Dillon Beliveau 2022-06-18 16:00:22 -07:00
  • 1963fb2c22 RSP fixes in LTV, RSQ Dillon Beliveau 2022-06-18 15:13:48 -07:00
  • a38a9a3482 cart read 8/16 bit fixes, don't use bus functions for DMAs Dillon Beliveau 2022-06-18 13:46:46 -07:00
  • a746ea2948 Fix initial value of $Status Dillon Beliveau 2022-06-18 12:58:10 -07:00
  • c4bfe82617 TLB fixes Dillon Beliveau 2022-06-18 12:58:04 -07:00
  • 749d8ade0c Exception handling fixes Dillon Beliveau 2022-06-18 12:57:49 -07:00
  • 70e12f5a4a Add libgtk-3-dev to dependencies Dillon Beliveau 2022-06-16 20:21:27 -07:00
  • 8fc5c73bb7
         Remove imfilebrowser.h from contrib/imgui/CMakeLists.txt Dillon Beliveau 2022-06-15 15:43:23 -07:00
  • d7e09d88ab Switch to nativefiledialog-extended for opening ROMs Dillon Beliveau 2022-06-14 21:59:07 -07:00
  • 9ebc6a101d
         Correct default COP0.Status value for PIF HLE (#26) Simone Coco 2022-06-14 23:19:19 +02:00
  • e69522a135 Correct default COP0.Status value for PIF HLE CocoSimone 2022-06-14 23:18:26 +02:00
  • f96e2e546a this is not a 32 bit function Dillon Beliveau 2022-06-12 23:10:18 -07:00
  • 5c61af5795 mask entry_hi.vpn2 with page_mask on tlbwi Dillon Beliveau 2022-06-12 23:09:36 -07:00
  • 18da8eab9c TLB updates, properly use region when matching VPNs Dillon Beliveau 2022-06-12 22:47:30 -07:00
  • 799e9a51a9 Cleanup bus a bit Dillon Beliveau 2022-06-12 19:53:18 -07:00
  • 2c1bf778f2 fix LL, LLD, SC, SCD Dillon Beliveau 2022-06-12 19:43:00 -07:00
  • c4ea8a3ed5 many small fixes, including separate memory map for user mode Dillon Beliveau 2022-06-12 19:17:25 -07:00
  • dda8b64b84 minor fixes Dillon Beliveau 2022-06-12 17:17:09 -07:00
  • 88124bf109 test both interpreter and recompiler with cpu test roms Dillon Beliveau 2022-06-12 17:16:36 -07:00
  • 1086380ea6 Fix compiler warning Dillon Beliveau 2022-06-12 15:58:13 -07:00
  • 9a897700a2 these are correct Dillon Beliveau 2022-06-12 15:56:58 -07:00
  • 6fc1536c06 Comments in r4300i_handle_exception Dillon Beliveau 2022-06-12 15:12:58 -07:00
  • 10c8477e6b TLB exceptions in more instructions, alignment checks Dillon Beliveau 2022-06-12 15:10:19 -07:00
  • 6032c4662d Rework TLB functions, fix TLBP instruction Dillon Beliveau 2022-06-12 14:25:57 -07:00
  • b0a5d646ba use coprocessor error 0 instead of -1 everywhere Dillon Beliveau 2022-06-12 13:58:06 -07:00
  • a651fa955c fix SSV for unaligned elements Dillon Beliveau 2022-06-11 20:30:32 -07:00
  • c44d4e7f64 CFC2 and CTC2 correct behavior for invalid indices Dillon Beliveau 2022-06-11 19:55:13 -07:00
  • 50cc6bb969 wrap RSP accesses around the end of DMEM Dillon Beliveau 2022-06-11 19:36:43 -07:00
  • e6f2ad07dc Fix RSP link instructions when branch depends on value of LR Dillon Beliveau 2022-06-11 19:29:37 -07:00
  • a8f6884817 fix RSP semaphore register Dillon Beliveau 2022-06-11 19:21:47 -07:00
  • dcc97e864e overflow exceptions in SUB and DSUB Dillon Beliveau 2022-06-11 18:47:22 -07:00
  • 6977a0cfef Only raise/lower SP interrupts if only one bit is set Dillon Beliveau 2022-06-11 18:32:53 -07:00
  • 9c2d235c30 COP0 open bus Dillon Beliveau 2022-06-11 18:30:12 -07:00
  • bc6be21d88 save reg, link, check condition to ensure LR is set correctly in BGEZALL Dillon Beliveau 2022-06-11 18:20:42 -07:00
  • befc6ad8a4 Condition is checked before link Dillon Beliveau 2022-06-11 17:46:41 -07:00
  • c62016aaf9 Simplify TLB registers' masking code Dillon Beliveau 2022-06-11 17:42:07 -07:00
  • b6d51f07af quiet! Dillon Beliveau 2022-06-11 17:17:05 -07:00
  • 8576eaafde Simplify page mask masking logic Dillon Beliveau 2022-06-11 16:41:50 -07:00
  • f7969a8444 replace load/store bools with bus_access_t enum Dillon Beliveau 2022-06-11 16:37:00 -07:00
  • 9295edb8e1 TLB miss exceptions in LH Dillon Beliveau 2022-06-11 16:28:50 -07:00
  • 8d40b774ab Unused CP0 registers are a single register Dillon Beliveau 2022-06-11 15:46:11 -07:00
  • 47840896fe CKSEG3 Dillon Beliveau 2022-06-11 15:26:33 -07:00
  • b9e4a0e1e2 reserved instruction exception Dillon Beliveau 2022-06-11 15:26:22 -07:00
  • 1d15877f3b Support for TLB exceptions in more instructions, implement XKSEG Dillon Beliveau 2022-06-11 15:12:44 -07:00
  • 2bd0c760fb TLB exceptions in LL Dillon Beliveau 2022-06-11 14:51:37 -07:00
  • ea2d27b447 more TLB fixes Dillon Beliveau 2022-06-11 14:50:12 -07:00
  • f7400a7438 TLB fixes Dillon Beliveau 2022-06-11 14:02:04 -07:00
  • 92b94ecc08 TLBR reads page mask Dillon Beliveau 2022-06-11 12:33:14 -07:00
  • bca5d22733 typo Dillon Beliveau 2022-06-11 11:53:52 -07:00
  • 5fd3da320f fix some cop0 masking and the random/wired registers Dillon Beliveau 2022-06-11 10:42:50 -07:00
  • 8ef29e1b8d fix test_cpu Dillon Beliveau 2022-06-10 20:46:58 -07:00
  • bed9a97b7c Set prev branch flag when needed in dynarec Dillon Beliveau 2022-06-10 20:42:15 -07:00
  • 7ca66ccf9f Set and use branch_likely_taken flag in dynarec instead of piggybacking on branch flag Dillon Beliveau 2022-06-10 20:33:07 -07:00
  • 92dbfbd5a9 fix exceptions inside branch delay slots Dillon Beliveau 2022-06-10 19:37:06 -07:00
  • 4978d2a15a fix ai address increment Dillon Beliveau 2022-06-09 22:40:37 -07:00
  • c844f9bc73 fix signed overflow check to be more reliable Dillon Beliveau 2022-06-06 01:11:28 -07:00
  • 59649b1601 bad_vaddr is read only Dillon Beliveau 2022-06-06 00:37:40 -07:00
  • 63ad3ea449 address error fixes, context/xcontext masking on writes Dillon Beliveau 2022-06-05 23:59:57 -07:00
  • 2da81b073e address errors in SW Dillon Beliveau 2022-06-05 22:49:33 -07:00
  • f109365215 fix address error exceptions Dillon Beliveau 2022-06-05 22:38:13 -07:00
  • 7843efe895 fix cast Dillon Beliveau 2022-06-05 16:22:06 -07:00
  • 718a8ec3cf don't logalways Dillon Beliveau 2022-06-05 15:31:39 -07:00
  • 3ed1ec641e fix 64 bit CAUSE writes, set coprocessor_error to zero in CAUSE when the error is not with any coprocessor Dillon Beliveau 2022-06-05 15:19:53 -07:00
  • da54e19af6 more TRAP instructions Dillon Beliveau 2022-06-05 15:16:26 -07:00
  • fc02b2a078 TLB exceptions in SW Dillon Beliveau 2022-06-05 14:28:56 -07:00
  • 40afb9c887 remove asserts, implement/stub a few things to get n64-systemtest sans TLB/trap tests to run with the interpreter Dillon Beliveau 2022-06-05 14:20:13 -07:00
  • 68a0c186d2 latest version of tests Dillon Beliveau 2022-01-16 14:37:47 -08:00
  • 447c0c89a1 mask cl in srav in jit Dillon Beliveau 2022-01-16 14:08:24 -08:00
  • f3cd487021 generate rs,rt,rd tests Dillon Beliveau 2022-01-16 14:08:11 -08:00
  • 0af9953335 fix sra/srav in jit as well Dillon Beliveau 2022-01-15 17:07:49 -08:00
  • 1dce496991 Support generating shift test cases, fix sra and srav Dillon Beliveau 2022-01-15 16:51:16 -08:00
  • 15b83f49db
         Update link to compatibility list Dillon Beliveau 2022-01-08 15:16:04 -05:00
  • e93e3ddabe shift rsp pc correctly when reading from the CPU Dillon Beliveau 2022-01-08 11:50:34 -08:00
  • 25cbbc71b1 move ERET to mips_instructions.c Dillon Beliveau 2021-12-28 17:22:43 -08:00
  • 84472154f9
         Fix CI on the latest commit (#22) Simone Coco 2021-12-29 01:15:54 +01:00
  • 381a7dd6e7 attempt to fix CI simuuz 2021-12-29 01:11:56 +01:00
  • a90846f349 attempt to fix CI simuuz 2021-12-29 00:44:13 +01:00
  • 56e2f678c4 attempt to fix CI simuuz 2021-12-29 00:41:50 +01:00
  • fc851e5f54 Maintain aspect ratio when resizing window Dillon Beliveau 2021-12-19 18:02:26 -08:00
  • 2d66075ec1 Compile blit shaders instead of hardcoding Dillon Beliveau 2021-12-19 17:06:52 -08:00
  • 6bc057f789 Remove an old obsolete TODO Dillon Beliveau 2021-11-13 15:26:21 -08:00
  • 2e4676b915 Merge branch 'reset-button' Dillon Beliveau 2021-11-06 11:11:46 -07:00
  • f975d5bdff Add -g to debug builds Dillon Beliveau 2021-11-06 11:02:25 -07:00