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  • ffe720bb65 sb, blez Dillon Beliveau 2023-02-14 21:59:08 -08:00
  • 213fde13ca fix less than and greater than conditions Dillon Beliveau 2023-02-14 21:54:35 -08:00
  • cac306a042 breakpoints in v2 compiler Dillon Beliveau 2023-02-14 21:54:07 -08:00
  • d25da46e4a block browser improvements Dillon Beliveau 2023-02-14 21:53:31 -08:00
  • ee4d709b53 cfc1, ctc1, ignore FPU instructions Dillon Beliveau 2023-02-12 21:42:48 -08:00
  • 2fd89ed5e5 compile set cp0 status Dillon Beliveau 2023-02-12 19:37:23 -08:00
  • 70b9a50e50 Distinguish valid immediates from constants in the compiler. Compile MFC0 Dillon Beliveau 2023-02-12 18:18:48 -08:00
  • b297034494 check registers in host emitters Dillon Beliveau 2023-02-12 18:10:18 -08:00
  • 1e553cebbb DSLL, DSLL32, DSRA, DSRA32, SRA, SRAV, DSLLV, NOR, XORI, SLTI, SLTIU Dillon Beliveau 2023-02-12 16:15:00 -08:00
  • 4d7d9666ab fix ir_emit_link Dillon Beliveau 2023-02-12 16:13:09 -08:00
  • b9bb72eb56 DADDIU Dillon Beliveau 2023-02-12 15:08:20 -08:00
  • deb17652a8 LWU and DADDI Dillon Beliveau 2023-02-12 15:06:37 -08:00
  • f0025cb5b7 handle const conditions in cond block exit, fix branch likely cond negation, implement BEQL Dillon Beliveau 2023-02-12 15:04:38 -08:00
  • 95bf422688 don't allow binding r0 to a value Dillon Beliveau 2023-02-12 14:16:06 -08:00
  • 804ed3d702 fix types for VALUE_TYPE_U16 Dillon Beliveau 2023-02-12 14:15:56 -08:00
  • fac8224a3f move v2_link_and_encode into a separate TU Dillon Beliveau 2023-02-12 14:15:39 -08:00
  • 00a407c00e fill out entire block struct from within v2_link_and_encode Dillon Beliveau 2023-02-12 13:46:06 -08:00
  • 37eb87e3ad missing_block_handler not static Dillon Beliveau 2023-02-12 13:43:38 -08:00
  • 9f2b323fae not static, unique names Dillon Beliveau 2023-02-12 13:35:27 -08:00
  • 47ad0a4e12 updates to unimplemented cases in v2_compiler Dillon Beliveau 2023-02-12 10:20:24 -08:00
  • 1003a7a397 compare tool fixes Dillon Beliveau 2023-02-12 10:18:27 -08:00
  • b964012d7e subtraction fixes Dillon Beliveau 2023-02-12 10:18:13 -08:00
  • ff5f223d89 missing prototype Dillon Beliveau 2023-02-11 22:14:10 -08:00
  • a84394893b bgezal Dillon Beliveau 2023-02-11 22:12:40 -08:00
  • 7f4cde5fab or/xor with two variable args Dillon Beliveau 2023-02-11 22:06:17 -08:00
  • 3ed0f82607 XOR, SUBU, SLLV, SRLV Dillon Beliveau 2023-02-11 22:01:11 -08:00
  • 40a1af4201 fix various dynarec bugs Dillon Beliveau 2023-02-11 21:03:25 -08:00
  • 9925f84572 dynarec_compare tool Dillon Beliveau 2023-02-11 21:02:21 -08:00
  • 2d7886697b preprocessor macro INSTANT_PI_DMA for debugging Dillon Beliveau 2023-02-11 21:01:05 -08:00
  • decc017b84 IR multiplies, MULTU Dillon Beliveau 2023-02-11 18:10:29 -08:00
  • af878c9af4 remove hardcoded reg nums Dillon Beliveau 2023-02-11 15:24:35 -08:00
  • 0f83d009c2 C functions to dump disassembly Dillon Beliveau 2023-02-11 15:18:01 -08:00
  • 50da5291ff optimize more memory accesses to use offsets when possible Dillon Beliveau 2023-02-11 15:14:38 -08:00
  • 5fc06a9625 block disassembly viewer imgui Dillon Beliveau 2023-02-11 14:38:50 -08:00
  • 7c047b5983 Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-02-11 12:22:08 -08:00
  • 0ca38c593b Upgrade imgui and implot Dillon Beliveau 2023-02-11 12:21:05 -08:00
  • 9ebc767db3 optimize host_emit_mov_mem_reg to use an offset into N64CPU if possible Dillon Beliveau 2023-02-11 11:15:06 -08:00
  • 3a4b0b6d0e
         Move setup-nasm action to top level Dillon Beliveau 2023-02-06 09:41:36 -08:00
  • 77431e74dc
         Install nasm in github actions Dillon Beliveau 2023-02-06 09:36:28 -08:00
  • 67d777c78f AND two variable values Dillon Beliveau 2023-02-05 19:11:08 -08:00
  • 0f1feb3a40 flush registers when block exited early Dillon Beliveau 2023-02-05 19:01:25 -08:00
  • c99533ee8d finish exit block early test, broken implementation Dillon Beliveau 2023-02-05 18:02:43 -08:00
  • 80581dd926 compiled not, start working on likely branches, start setting up unit tests for dynarec Dillon Beliveau 2023-02-05 17:18:06 -08:00
  • b59d55c80b sltu, and, or, nop cache Dillon Beliveau 2023-02-05 15:28:22 -08:00
  • b9f56d6820 Logging updates Dillon Beliveau 2023-02-05 15:10:43 -08:00
  • c230cff119 compiled or, not, mtc0, sanitizers not passed to nasm, reserve r12 for cpu pointer, flush regs as early as possible, const shift, Dillon Beliveau 2023-02-05 15:06:36 -08:00
  • 397beebe00 quiet down logs Dillon Beliveau 2023-02-05 02:34:23 -08:00
  • e4c37fca2c s8 -> fp Dillon Beliveau 2023-02-05 02:18:53 -08:00
  • 26fea58bb6 srl, lb, bgtz, addi Dillon Beliveau 2023-02-05 02:18:45 -08:00
  • 9865dbc16a jit crashes on TLB MISS PC for now Dillon Beliveau 2023-02-05 02:17:00 -08:00
  • b6d87f0412 sh, sd, lbu, lh, j, jal, addu, slt + propagate constants for check condition & set_cond_exit_pc Dillon Beliveau 2023-02-05 00:32:51 -08:00
  • 1ef1638734 beq Dillon Beliveau 2023-02-05 00:02:20 -08:00
  • 7374781840 addiu Dillon Beliveau 2023-02-04 23:51:16 -08:00
  • 9d1372058a fix block->run call Dillon Beliveau 2023-02-04 23:50:31 -08:00
  • a19dd6c08d fix register allocation Dillon Beliveau 2023-02-04 23:50:04 -08:00
  • f51bd073e6 fix stack alignment Dillon Beliveau 2023-02-04 23:49:47 -08:00
  • 06a7e55d4c Crash when unable to match address to region Dillon Beliveau 2023-02-04 22:50:36 -08:00
  • 027f87eebc Wrong type Dillon Beliveau 2023-02-04 22:48:45 -08:00
  • c9e2318e88 sll, jalr, add Dillon Beliveau 2023-02-04 21:23:29 -08:00
  • ecba2a94ac lhu, ld, jr Dillon Beliveau 2023-02-04 19:55:38 -08:00
  • d4ddbd6378 Better (but very inefficient) register allocation by calculating lifetimes Dillon Beliveau 2023-02-04 17:19:53 -08:00
  • 96e18a966d Don't use RSP for register allocation Dillon Beliveau 2023-02-04 17:17:16 -08:00
  • ce0d291596 compile ADD & TLB_LOOKUP Dillon Beliveau 2023-02-04 17:16:24 -08:00
  • f4cf4ea39a Load guest reg set by another block Dillon Beliveau 2023-02-04 16:15:25 -08:00
  • 93a11f4252 flush guest regs at the end of the block Dillon Beliveau 2023-02-04 16:01:39 -08:00
  • a995a900d6 temporary "dispatcher" in ASM - wrap block thunks in an ASM function Dillon Beliveau 2023-02-04 15:25:43 -08:00
  • 697434a2f4 check condition, set exit pc Dillon Beliveau 2023-02-04 14:05:26 -08:00
  • 0c6ccdd3ce compile IR_AND Dillon Beliveau 2023-01-29 16:17:28 -08:00
  • b791cd691a begin work on x86_64 emitter Dillon Beliveau 2023-01-29 16:00:21 -08:00
  • 70ece93da6 TLB lookup IR instruction Dillon Beliveau 2023-01-29 14:19:43 -08:00
  • b640c14287 asm_emitter -> v1_emitter Dillon Beliveau 2023-01-29 12:58:21 -08:00
  • 31b2edb26a minimum viable register allocation Dillon Beliveau 2023-01-29 12:56:23 -08:00
  • 0581de8f44 Only print when actually allocating a guest reg Dillon Beliveau 2023-01-29 11:15:01 -08:00
  • e68656f665 Document functions in target_platform, add is_valid_immediate() Dillon Beliveau 2023-01-29 11:10:08 -08:00
  • b3d8b285c3 Rework IR storage to use a linked list and pointers instead of indices Dillon Beliveau 2023-01-29 11:08:47 -08:00
  • 87d51c5c47 remove unused Dillon Beliveau 2023-01-28 16:01:29 -08:00
  • 3f3ef2622e Enable -Werror=switch Dillon Beliveau 2023-01-28 16:01:17 -08:00
  • d343bb7370 shrink constants Dillon Beliveau 2023-01-28 14:44:54 -08:00
  • 392fa1379c fix for values mapped to registers, add todo comment Dillon Beliveau 2023-01-28 14:13:36 -08:00
  • 6f3bacb310 constant propagation and dead code elimination Dillon Beliveau 2023-01-28 13:31:07 -08:00
  • 1613bd46aa helpers for ir_emit_set_constant, documentation comments Dillon Beliveau 2023-01-28 12:25:50 -08:00
  • b372cff267 abstract away common branch code Dillon Beliveau 2023-01-28 12:15:29 -08:00
  • 30b650ec19 don't print v%d= where it doesn't make sense Dillon Beliveau 2023-01-28 12:07:20 -08:00
  • 7a0f66431c More IR instructions, handle branches Dillon Beliveau 2023-01-28 11:58:35 -08:00
  • aa3b9e10d7 print IR as string Dillon Beliveau 2023-01-22 17:15:12 -08:00
  • 6a224a1639 don't load extra zero constants Dillon Beliveau 2023-01-22 15:26:16 -08:00
  • 9e2f050ee9 andi Dillon Beliveau 2023-01-22 14:30:25 -08:00
  • e08943d3e9 loads, refactor out common code between load/store Dillon Beliveau 2023-01-22 14:27:08 -08:00
  • 4a17f2e2d4 implement a few more instructions Dillon Beliveau 2023-01-16 17:40:33 -08:00
  • 850c93e292 missed a file Dillon Beliveau 2023-01-16 15:34:08 -08:00
  • 3e861d123f emit IR for LUI Dillon Beliveau 2023-01-16 15:10:27 -08:00
  • 3a1d5e952f framework out the IR emitter Dillon Beliveau 2023-01-16 12:37:29 -08:00
  • c70b2feaed remove logging and crash Dillon Beliveau 2023-01-14 16:00:04 -08:00
  • ae58d464f0 handle determining which instructions should be compiled into a block Dillon Beliveau 2023-01-14 14:29:48 -08:00
  • 1b66e11e43 refactor jit components I plan on rewriting to a new module Dillon Beliveau 2023-01-07 14:25:03 -08:00
  • e8f553e76e
         Add CodeQL workflow for GitHub code scanning LGTM Migrator 2022-12-08 17:12:57 +00:00
  • 2dd8f0b60f dpc start should never change Dillon Beliveau 2022-10-16 10:18:27 -07:00
  • bd4ff4a3c2 fix DIV and DDIV Dillon Beliveau 2022-10-16 09:58:34 -07:00
  • 6cdc45c460 Support capstone dependency on windows Dillon Beliveau 2022-10-09 18:23:09 -07:00
  • c1b7c8169d Some WIP things Derek "Turtle" Roe 2022-10-06 04:00:54 -05:00