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  • f1d1f5106a WIP Dillon Beliveau 2023-03-10 18:49:59 -08:00
  • c91aac0bee Update error message Dillon Beliveau 2023-03-07 23:18:15 -08:00
  • 55dea4fcb2 remove nasm Dillon Beliveau 2023-03-07 10:52:14 -08:00
  • 390175bafd dynarec prologue/epilogue fixes, dangling pointer fix Dillon Beliveau 2023-03-07 09:52:05 -08:00
  • 35694c7842 statically allocate dynarec Dillon Beliveau 2023-03-07 00:50:35 -08:00
  • c75cecb156 macro for function prologue and epilogue Dillon Beliveau 2023-03-06 23:10:28 -08:00
  • 870cc35c8f don't disassemble run_block Dillon Beliveau 2023-03-06 23:10:13 -08:00
  • c7a6503bd9 set run block fp inside init function Dillon Beliveau 2023-03-06 23:01:26 -08:00
  • 336f4c21b7 Many dynarec fixes, partially to work around a strange stack corruption issue seeming to come from dynasm Dillon Beliveau 2023-03-06 22:59:17 -08:00
  • bbea593d54 fix issue with loading settings Dillon Beliveau 2023-03-06 22:26:49 -08:00
  • 9475b6570b emit dispatcher at runtime Dillon Beliveau 2023-03-06 00:01:39 -08:00
  • 4521eeaa36 common min/max functions Dillon Beliveau 2023-03-04 18:44:19 -08:00
  • 013f04c9e4 more fpu compares Dillon Beliveau 2023-03-04 17:58:50 -08:00
  • 1ac424d986 64 bit multiplies and divides, spilling fixes, cp0 stuff Dillon Beliveau 2023-03-04 17:51:08 -08:00
  • 33cd06ba91 oops Dillon Beliveau 2023-03-05 12:47:07 -08:00
  • b4a9ec4c9c handle consts more in mults and divs Dillon Beliveau 2023-03-05 12:43:57 -08:00
  • 0b6c26be4f cleanup Dillon Beliveau 2023-03-04 17:49:10 -08:00
  • 78d96889e8 CMAKE_SYSTEM_PROCESSOR is AMD64 on 64 bit Windows Dillon Beliveau 2023-03-04 17:48:58 -08:00
  • 8fae77d346 mkdir dynarec_v2_tests before building file into it Dillon Beliveau 2023-03-04 17:46:50 -08:00
  • 41bd14bd6e print cwd when test_dynarec_v2 fails to open code file Dillon Beliveau 2023-03-04 17:28:09 -08:00
  • 668b843f3e dadd, daddu, dsub, dsubu, spilling fixes Dillon Beliveau 2023-03-04 16:46:14 -08:00
  • 18f37d593b spilling fixes Dillon Beliveau 2023-03-04 16:31:06 -08:00
  • b6d3f50bbc trunc double->word Dillon Beliveau 2023-03-04 16:07:46 -08:00
  • 1c48d6f5ab blezl, float lt compare, bc1t, bc1f, bc1fl Dillon Beliveau 2023-03-04 16:02:08 -08:00
  • 567da2fd81 handle spilled cond reg Dillon Beliveau 2023-03-04 15:55:41 -08:00
  • 7cf1094afb mult Dillon Beliveau 2023-03-04 15:55:32 -08:00
  • a3705f4186 subtraction with reg - imm Dillon Beliveau 2023-03-04 15:38:23 -08:00
  • 98aad3f509 fpu mov Dillon Beliveau 2023-03-04 15:26:02 -08:00
  • 29d5a5ef74 log block size in all cases Dillon Beliveau 2023-03-04 15:25:31 -08:00
  • bf27db8ab2 fix NOT constant propagation, improve constant shrinking Dillon Beliveau 2023-03-04 15:24:50 -08:00
  • baa75790ae mult u32 reg reg Dillon Beliveau 2023-03-04 14:38:19 -08:00
  • 615c4adb84 better calculation of what instructions to put into a block Dillon Beliveau 2023-03-04 14:31:06 -08:00
  • fd8539962a trunc Dillon Beliveau 2023-03-04 14:27:47 -08:00
  • 9c4a97aa07 a few minor fixes Dillon Beliveau 2023-03-04 14:27:28 -08:00
  • 0d3dc5bb3f mfc1 Dillon Beliveau 2023-03-01 00:49:41 -08:00
  • 7fa0c7019f convert float types with different modes Dillon Beliveau 2023-03-01 00:44:51 -08:00
  • f268d956bf float cmp, sub Dillon Beliveau 2023-03-01 00:32:42 -08:00
  • 06e58f7089 fix loading FGRs at the beginning of blocks Dillon Beliveau 2023-03-01 00:32:22 -08:00
  • ba742d41da compile float addition Dillon Beliveau 2023-02-28 23:16:37 -08:00
  • 2379544b5f float constants Dillon Beliveau 2023-02-28 23:10:55 -08:00
  • 6d55d6ee8a more stubs, implement float divides Dillon Beliveau 2023-02-28 22:36:10 -08:00
  • 7322b56a9d determine type Dillon Beliveau 2023-02-28 22:18:52 -08:00
  • 8a6b355cbf fixes, stub float subtraction Dillon Beliveau 2023-02-28 22:17:50 -08:00
  • f4a02719e6 stub ir_float_check_condition, implement bc1tl Dillon Beliveau 2023-02-28 22:03:56 -08:00
  • 602b15e914 stub floating point divides and adds Dillon Beliveau 2023-02-27 00:23:54 -08:00
  • 0cc0b890e6 swc1, fix fgrs being reused for smaller values, emit cvt instructions Dillon Beliveau 2023-02-26 18:02:13 -08:00
  • 819659e510 LDC1, SDC1 Dillon Beliveau 2023-02-26 15:36:04 -08:00
  • 5d155dbfb2 fix bug in register flushing Dillon Beliveau 2023-02-26 15:35:09 -08:00
  • 5ae2b28272 lwc1, cp1 cvt instructions Dillon Beliveau 2023-02-26 15:06:51 -08:00
  • fd39ae898d handle consts in mov_reg_type Dillon Beliveau 2023-02-26 10:40:57 -08:00
  • 13fb1d6edb remove printfs Dillon Beliveau 2023-02-25 18:36:20 -08:00
  • 11dbb2be39 print_ir_block in header Dillon Beliveau 2023-02-25 17:50:34 -08:00
  • 380a9a1977 stub FPU IR emitters Dillon Beliveau 2023-02-25 17:48:59 -08:00
  • 4b2d2118f1 nicer output formatting Dillon Beliveau 2023-02-25 17:48:23 -08:00
  • 71d406fd8c fix warnings Dillon Beliveau 2023-02-25 17:48:10 -08:00
  • 94cf6af256 flush FPU registers Dillon Beliveau 2023-02-25 17:30:29 -08:00
  • 029996c025 fix test Dillon Beliveau 2023-02-24 17:52:29 -08:00
  • b442ea894a allocate FPU registers Dillon Beliveau 2023-02-24 17:45:59 -08:00
  • 8678084991 remove logfatal Dillon Beliveau 2023-02-22 00:17:58 -08:00
  • 40bcfe6257 oops Dillon Beliveau 2023-02-20 16:54:26 -08:00
  • e69edd528c macro for blockcache outer index Dillon Beliveau 2023-02-20 16:25:29 -08:00
  • 81de6a8638 fix coprocessor instruction decoding Dillon Beliveau 2023-02-20 16:21:25 -08:00
  • 950c557c19 print IR when difference found Dillon Beliveau 2023-02-20 15:51:52 -08:00
  • c9b5ac6296 refactor interpreter to allow running the CPU for more than a single cycle at a time Dillon Beliveau 2023-02-20 15:33:04 -08:00
  • 5c3cd84b5e timing slightly more accurate in n64_system_step Dillon Beliveau 2023-02-20 13:14:39 -08:00
  • 5034d33fd3 ldl, ldr Dillon Beliveau 2023-02-20 03:20:43 -08:00
  • 759f633c0f don't expand notted consts Dillon Beliveau 2023-02-20 02:47:08 -08:00
  • 317b701f28 swl, swr, empty emitters for ldl, ldr, sdl, sdr Dillon Beliveau 2023-02-20 02:46:06 -08:00
  • 54f2e7658c lwl/lwr Dillon Beliveau 2023-02-20 02:41:00 -08:00
  • 6c0ac17d8d bltzl, bgtzl Dillon Beliveau 2023-02-20 00:25:14 -08:00
  • 006c99c8a4 mfc0 compare, count Dillon Beliveau 2023-02-20 00:11:23 -08:00
  • 8d6da6281f bgezl Dillon Beliveau 2023-02-20 00:11:12 -08:00
  • f934dc0b6c s32 multiplies Dillon Beliveau 2023-02-20 00:11:04 -08:00
  • 44b71566a6 cmp reg, imm works with spilled values Dillon Beliveau 2023-02-20 00:10:55 -08:00
  • b13c557498 split FPU emitters into a separate source file Dillon Beliveau 2023-02-20 00:10:41 -08:00
  • f3e794a6e5 fix and reg, imm with spilled reg Dillon Beliveau 2023-02-19 16:41:18 -08:00
  • d9bc1d4c7c color coded dynarec_compare output Dillon Beliveau 2023-02-19 15:16:08 -08:00
  • 94e26dafcf cleanup output of dynarec_compare Dillon Beliveau 2023-02-19 14:55:26 -08:00
  • 26a9404ec1 support reading EPC Dillon Beliveau 2023-02-19 14:55:17 -08:00
  • 19bdc159fa add reg, reg works with spilled registers Dillon Beliveau 2023-02-19 14:55:03 -08:00
  • 29eb052d7a IR_SET_PTR compiles correctly Dillon Beliveau 2023-02-19 14:44:28 -08:00
  • d7d013a8a0 fix IR_SET_PTR always being optimized out Dillon Beliveau 2023-02-19 14:44:03 -08:00
  • c2cabea407 eret Dillon Beliveau 2023-02-19 14:27:07 -08:00
  • c9c28c60e5 dynarec_compare pick rom entrypoint as beginning of comparison Dillon Beliveau 2023-02-19 04:14:12 -08:00
  • c9cca55226 replace get_mult_result with get_ptr, add mthi, mfc0 fixes and additions, more const shifts, stack alignment Dillon Beliveau 2023-02-19 04:14:00 -08:00
  • a11cda4f1f mfc0 cause, cmp reg reg for spilled regs, flush spilled regs Dillon Beliveau 2023-02-19 03:36:39 -08:00
  • 6c1108622d sub const, reg Dillon Beliveau 2023-02-19 03:28:08 -08:00
  • b3ff77df84 dynasm 1.4.0 -> 1.5.0 Dillon Beliveau 2023-02-19 03:16:02 -08:00
  • f2f115ce1f constant propagation for logical right shift 32 bit Dillon Beliveau 2023-02-18 21:25:36 -08:00
  • 4cf8825581 remove CP0-specific IR instructions, add bgez, more mfc0 and mtc0 stuff Dillon Beliveau 2023-02-18 21:21:41 -08:00
  • 1e46858246 MTC0 stuff, ignore TLBWI Dillon Beliveau 2023-02-18 21:00:11 -08:00
  • b1a66e7da4 alloc spilled register correctly Dillon Beliveau 2023-02-18 20:59:42 -08:00
  • 6a3a206269 oops Dillon Beliveau 2023-02-18 20:41:25 -08:00
  • c0c1f1af6d bltz should not link Dillon Beliveau 2023-02-18 20:39:55 -08:00
  • 4c268f80d2 dynarec_compare improvements: copy sp dmem and imem, vi timing and interrupts Dillon Beliveau 2023-02-18 20:39:44 -08:00
  • 1618062a91 div, more spilled reg handling Dillon Beliveau 2023-02-18 19:44:39 -08:00
  • 29492f76f9 register allocation fixes, mult with two variable regs, handle spilled regs in more cases Dillon Beliveau 2023-02-18 17:54:30 -08:00
  • d9832061ff pass full register allocation information to emitters, spill to stack Dillon Beliveau 2023-02-18 16:30:36 -08:00
  • 5633bf4431 Rewrite register allocation algorithm Dillon Beliveau 2023-02-18 14:03:35 -08:00
  • 3c22197660 bltz, mult, sub Dillon Beliveau 2023-02-15 23:56:11 -08:00