Emulation/n64
1
0
Fork 0
mirror of https://github.com/Dillonb/n64.git synced 2025-04-02 10:42:08 -04:00
Code Issues Projects Releases Packages Wiki Activity

Commit graph

  • 6b7ed7941c Get register type properly Dillon Beliveau 2023-04-23 19:22:31 -07:00
  • f76ad08062 CP0 regs + TLB instructions, enough to get GoldenEye working Dillon Beliveau 2023-04-23 16:28:53 -07:00
  • f37d9fc568 Sort block list so matching sysconfig is at the head when a miss occurs Dillon Beliveau 2023-04-18 22:41:57 -07:00
  • 1b3e930857 spilled support for xor imm Dillon Beliveau 2023-04-16 15:49:20 -07:00
  • a79631314e remove breakpoint Dillon Beliveau 2023-04-16 15:05:52 -07:00
  • 2465812502 fix a bug in DIV Dillon Beliveau 2023-04-16 14:44:54 -07:00
  • b9801847ed dynarec compare fixes + support for tas movies Dillon Beliveau 2023-04-16 14:44:46 -07:00
  • ce598123d0 cop1 unusable exceptions are implemented in the jit now Dillon Beliveau 2023-04-15 12:23:07 -07:00
  • 8c81117c73 more float conversions Dillon Beliveau 2023-04-15 12:17:49 -07:00
  • 01b41aaeda detect and handle branch in branch delay slot Dillon Beliveau 2023-04-09 15:43:43 -07:00
  • 73f234b76a implement more MFC0 and DMFC0 registers Dillon Beliveau 2023-04-09 15:24:53 -07:00
  • bc2c546668 compare u32 immediate fixes Dillon Beliveau 2023-04-09 15:24:30 -07:00
  • a43437f63e division improvements Dillon Beliveau 2023-04-09 15:24:19 -07:00
  • bba290b97e spilled reg handling in shifts Dillon Beliveau 2023-04-09 15:22:30 -07:00
  • 801c697bf6 dsrav Dillon Beliveau 2023-04-09 15:11:39 -07:00
  • 125e799ef9 set prev_branch = branch before handling TLB miss pc exception Dillon Beliveau 2023-04-09 12:49:40 -07:00
  • ff51ff3ad7 pass bus access correctly during constant propagation (even though it shouldn't matter) Dillon Beliveau 2023-04-09 12:36:48 -07:00
  • f5898fff12 check mult hi and mult lo in dynarec compare Dillon Beliveau 2023-04-09 12:22:22 -07:00
  • ef5b74aca6 FPU register behavior improvements Dillon Beliveau 2023-04-09 12:22:04 -07:00
  • 52530fb466 lld Dillon Beliveau 2023-04-09 10:29:43 -07:00
  • cf35a1d482 spilled reg handling in not_reg and add_reg_imm Dillon Beliveau 2023-04-09 10:18:09 -07:00
  • 40a95f83b5 ll, sc, improve conditional block exit instruction, Dillon Beliveau 2023-04-08 17:31:28 -07:00
  • 1a1ef04953 s64 multiply Dillon Beliveau 2023-04-08 13:23:59 -07:00
  • 59b37f750e unordered float compares, dsrlv, teq Dillon Beliveau 2023-04-08 10:48:14 -07:00
  • 6309dfa002 set epc, xcontext, and implement dmfc0 Dillon Beliveau 2023-03-27 18:04:50 -07:00
  • 0d1e7cf3e7 interpreter fallback when a delay slot is on a different page from its branch Dillon Beliveau 2023-03-27 18:04:08 -07:00
  • 276ccf9d95 use SSE2NEON macos-arm64 Dillon Beliveau 2023-03-22 11:57:09 -07:00
  • 330aaef32c ifdef'd out too much Dillon Beliveau 2023-03-22 11:49:05 -07:00
  • cd91e31a7f fixes for mac port, update parallel-rdp to a version supported by parallel-rdp Dillon Beliveau 2023-03-22 11:06:15 -07:00
  • 7a728522cc dmtc0 context/entryhi Dillon Beliveau 2023-03-19 20:37:48 -07:00
  • 25b2328ee9 check cp1 enabled Dillon Beliveau 2023-03-19 15:56:46 -07:00
  • 2ab8417dbc fix rom bounds checking Dillon Beliveau 2023-03-19 14:40:03 -07:00
  • dcc923ec61 "sysconfig" concept for jit blocks Dillon Beliveau 2023-03-19 14:39:55 -07:00
  • d6ecee8d87 more constant propagation for FPU ops Dillon Beliveau 2023-03-19 13:05:51 -07:00
  • 5a25741e6d improve mtc1/mfc1/dmtc1/dmfc1 Dillon Beliveau 2023-03-19 12:57:18 -07:00
  • 42664ae697 xor spilled regs Dillon Beliveau 2023-03-19 12:56:32 -07:00
  • b7cbccff3c handle spilled regs in mov_reg_imm and mult_reg_imm Dillon Beliveau 2023-03-19 02:14:04 -07:00
  • f1e434b345 make check_reg a macro, so that logfatals will link to the correct line Dillon Beliveau 2023-03-19 01:55:48 -07:00
  • b17ef7eb29 fix tests Dillon Beliveau 2023-03-19 01:43:11 -07:00
  • bf9c0a38a1 stub float round Dillon Beliveau 2023-03-19 01:37:56 -07:00
  • 2013b231df dsrl32, dmfc1, dmtc1, implement float_abs_reg_reg Dillon Beliveau 2023-03-19 01:23:32 -07:00
  • 89847bb47c sdl, sdr, sync, ll, sc Dillon Beliveau 2023-03-19 01:06:20 -07:00
  • b920127cfd clear FCR31 flag and cause in interpreter, when comparing Dillon Beliveau 2023-03-18 17:30:33 -07:00
  • 6932c7f383 check FCR31 in dynarec_compare Dillon Beliveau 2023-03-18 17:30:14 -07:00
  • d8ba707f4a Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-03-18 17:19:14 -07:00
  • a9071ba5b3 dynarec_compare: cleanup IPC resources at exit Dillon Beliveau 2023-03-18 16:56:02 -07:00
  • e267984840
         Merge pull request #39 from Dillonb/accurate_fpu Dillon Beliveau 2023-03-18 15:57:28 -07:00
  • bbd87af7d4 Fix FPU on Windows Dillon Beliveau 2023-03-18 15:52:01 -07:00
  • 1e3646457f mov.s is an alias for mov.d Dillon Beliveau 2023-03-18 15:13:34 -07:00
  • 2ffc72e187 sign extend when moving a 32 bit fpu reg to a gpr Dillon Beliveau 2023-03-18 15:11:49 -07:00
  • 28f15455b4 incomplete s64 divides Dillon Beliveau 2023-03-18 14:51:12 -07:00
  • ce699fe528 Explicit error when scheduler event nodes are exhausted Dillon Beliveau 2023-03-18 14:24:22 -07:00
  • 29f1f0a862 Remove extra on_pi_dma_complete() call Dillon Beliveau 2023-03-18 14:22:34 -07:00
  • 1c136e8d9c handle spilled GPR in mov_gpr_fgr Dillon Beliveau 2023-03-18 13:53:50 -07:00
  • 3191f95abd float sqrt/abs/neg Dillon Beliveau 2023-03-18 13:53:37 -07:00
  • ef02cf5500 when disassembling a block of guest code, print the instruction word Dillon Beliveau 2023-03-18 13:52:02 -07:00
  • b2803666d1 match JIT RSP behavior in interpreter, if we are comparing the jit vs. the interpreter Dillon Beliveau 2023-03-18 13:51:28 -07:00
  • ad04383c5d Fix mov reg_reg when both regs spilled Dillon Beliveau 2023-03-18 13:02:38 -07:00
  • 0fd0988189 Fix CVT overflow checks Dillon Beliveau 2023-03-18 11:29:31 -07:00
  • b701312282 set_cause_cvt_l_d takes a double Dillon Beliveau 2023-03-18 10:25:42 -07:00
  • 52bf0d8048 trunc.l, round.l, ceil.l, floor.l, cvt.l wip Dillon Beliveau 2023-03-13 00:05:52 -07:00
  • 71ccc8d94a trunc.w, round.w, ceil.w, floor.w, cvt.w complete Dillon Beliveau 2023-03-12 22:24:28 -07:00
  • 8b14b3d369 updates to trunc.w, round.w, ceil.w, floor.w, cvt.w. Not quite done yet Dillon Beliveau 2023-03-12 21:52:49 -07:00
  • 0bcf8902a8 cvt_w_s, cvt_w_d, remove last remaining NaN asserts Dillon Beliveau 2023-03-12 21:42:11 -07:00
  • 2e633dac5b cvt.s.fmt, cvt.d.fmt Dillon Beliveau 2023-03-12 21:12:31 -07:00
  • 0a8a014443 MFC1/DMFC1/MTC1/DMTC1 preserve cause Dillon Beliveau 2023-03-12 20:53:16 -07:00
  • 8574cc5f70 actually, this is the behavior of all invalid FPU operations Dillon Beliveau 2023-03-12 20:53:00 -07:00
  • 74d546c132 DCFC1/DCTC1 throw unimplemented exception Dillon Beliveau 2023-03-12 20:21:32 -07:00
  • be698f6486 all compare instructions Dillon Beliveau 2023-03-12 20:21:05 -07:00
  • 2e6ca46a9b exceptions and failure cases for mul/div/sqrt/abs/neg + fpu mov preserves cause Dillon Beliveau 2023-03-12 18:07:20 -07:00
  • 8bd11e1c05 handle FE_UNDERFLOW better Dillon Beliveau 2023-03-12 18:06:37 -07:00
  • ca9bf27f56 macro for FPU ops, use for add.s/d, sub.s/d Dillon Beliveau 2023-03-12 17:13:19 -07:00
  • 1152761f91 exceptions and failure cases for add.d Dillon Beliveau 2023-03-12 16:33:20 -07:00
  • 583ea15257 exceptions and failure cases for add.s Dillon Beliveau 2023-03-12 16:13:28 -07:00
  • bf820b2d96 fix FPU exceptions - unimplemented operation should always be enabled Dillon Beliveau 2023-03-12 14:05:43 -07:00
  • 5837f37998 implement ceil.l.d, ceil.w.d, floor.l.d, floor.w.d Dillon Beliveau 2023-03-12 14:05:30 -07:00
  • 9347c9cb61 fix 64 bit floating point register accesses Dillon Beliveau 2023-03-12 13:55:45 -07:00
  • 059fbf2bfa fix 32 bit floating point register accesses Dillon Beliveau 2023-03-12 13:25:51 -07:00
  • 72f46b462d Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-03-11 20:05:06 -08:00
  • 89bc6ed67d mov reg_reg with both regs spilled Dillon Beliveau 2023-03-11 19:51:42 -08:00
  • 3154f9eeeb tlbwi/tlbp Dillon Beliveau 2023-03-11 19:51:26 -08:00
  • fe2a97a80d FPU accuracy updates Dillon Beliveau 2023-03-11 17:53:21 -08:00
  • 665a1802fe improvements to fpu register access - not quite perfect yet Dillon Beliveau 2023-03-11 16:04:22 -08:00
  • 1b251a8075 check fpu exception Dillon Beliveau 2023-03-11 16:04:11 -08:00
  • 48d1cdae70 implement more floor instrs, implement ceil instrs Dillon Beliveau 2023-03-11 14:37:29 -08:00
  • 9cf8fb0c6e misaligned PC exceptions Dillon Beliveau 2023-03-11 14:11:04 -08:00
  • 8dadfebffa implement DSRL Dillon Beliveau 2023-03-11 13:40:44 -08:00
  • a028d0e96b fix DSUBU and DSUB Dillon Beliveau 2023-03-11 13:35:41 -08:00
  • dd2bc32c5d dynarec compare use shared memory for joybus devices Dillon Beliveau 2023-03-11 12:46:03 -08:00
  • 887a36fe2d Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-03-11 12:43:44 -08:00
  • ecbf11149f branch likely should only set bd flag when the branch is taken Dillon Beliveau 2023-03-11 12:41:14 -08:00
  • e62fb04403 check that interpreter and jit are in sync, zero cost exceptions Dillon Beliveau 2023-03-11 12:31:02 -08:00
  • 3028067b66 don't print IR if it's of the wrong block Dillon Beliveau 2023-03-11 11:47:13 -08:00
  • 0903f616b0 pc to exception log message Dillon Beliveau 2023-03-11 11:36:25 -08:00
  • 117650b924 quiet down logs Dillon Beliveau 2023-03-11 11:36:06 -08:00
  • a4626ed6a7 dynarec compare check cp0 Dillon Beliveau 2023-03-11 11:29:21 -08:00
  • 1c37494031 init settings in dynarec compare, only check vi interrupts when v_current changes, allow quitting in dynarec compare Dillon Beliveau 2023-03-11 11:10:45 -08:00
  • fe7b557495 disable CP1 exceptions when instant DMAs on Dillon Beliveau 2023-03-11 01:06:47 -08:00
  • e6fb45b1a7 INSTANT_PI_DMA -> INSTANT_DMA dynarec_v2_better_compare Dillon Beliveau 2023-03-11 01:01:57 -08:00
  • 6d7ab0e4d6 fix Dillon Beliveau 2023-03-11 00:49:55 -08:00