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  • 5c6a7b6a25 basic idle loop detection Dillon Beliveau 2023-08-25 20:23:38 -07:00
  • 28d0f790dd code to help me find idle loops Dillon Beliveau 2023-08-25 19:57:35 -07:00
  • d32d9c49ad minor fix, expand on comment Dillon Beliveau 2023-08-25 19:56:07 -07:00
  • 2b590aeb9a Include vulkan_headers.hpp first Dillon Beliveau 2023-08-24 20:27:05 -07:00
  • f35a4faf15 Merge branch 'dynarec_v2' Dillon Beliveau 2023-08-24 00:12:55 -07:00
  • 2d774afecb
         Merge pull request #38 from Dillonb/dynarec_v2 Dillon Beliveau 2023-08-24 00:12:14 -07:00
  • 4a229161ac make this a warning Dillon Beliveau 2023-08-23 23:58:58 -07:00
  • 0b9ff6bb0c register spilling rework Dillon Beliveau 2023-08-23 23:21:57 -07:00
  • 360c2e64be prep for register spilling rework Dillon Beliveau 2023-08-23 22:34:30 -07:00
  • 02e3c5be0c don't recalculate sysconfig every time dynarec_v2 Dillon Beliveau 2023-08-23 20:52:22 -07:00
  • 6a8141ec27 fix unlocking framerate on windows Dillon Beliveau 2023-08-23 20:51:04 -07:00
  • dd5e5d4bea split rsp link stage Dillon Beliveau 2023-08-22 01:26:59 -07:00
  • 6247ab3ee6 Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-08-22 01:26:06 -07:00
  • e65c6c553f Update parallel-rdp Dillon Beliveau 2023-08-21 21:47:10 -07:00
  • 1de8d567e8 Error check creating SDL resources Dillon Beliveau 2023-08-20 05:36:55 +00:00
  • 314d4c4f4d Only use SSE if available Dillon Beliveau 2023-08-20 05:36:28 +00:00
  • cb6e800dad send linux debug logs to stderr Dillon Beliveau 2023-08-08 23:44:06 -07:00
  • cccc33fd1b fix build when building without SIMD Dillon Beliveau 2023-08-05 12:25:23 -07:00
  • ec46e808b6 consistent naming Dillon Beliveau 2023-08-01 22:40:13 -07:00
  • cc12fd927a remove unused Dillon Beliveau 2023-08-01 22:40:04 -07:00
  • ebe665cb76 Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-07-29 14:24:41 -07:00
  • 3abd96f15a remove unused values Dillon Beliveau 2023-07-29 14:23:35 -07:00
  • 14acafda6b inline, add parens to silence warning Dillon Beliveau 2023-07-29 14:22:42 -07:00
  • 6e8652d79c reorder operations in sc and scd to match the interpreter Dillon Beliveau 2023-07-23 17:35:09 -07:00
  • 5cc3b49e3a check llbit in dynarec compare tool Dillon Beliveau 2023-07-23 17:26:15 -07:00
  • 0f48b25fea make the block's virtual address a compile time constant Dillon Beliveau 2023-07-23 16:36:30 -07:00
  • aab8bba894 disassemble guest code based on virtual address, not physical Dillon Beliveau 2023-07-22 22:07:05 -07:00
  • 1f0636e58e random number generation should be deterministic for both parent and child in dynarec compare tool Dillon Beliveau 2023-07-22 22:06:54 -07:00
  • c061b67c32 fix tlb exceptions when tlb_lookup destination reg is spilled Dillon Beliveau 2023-07-22 22:06:30 -07:00
  • 0a7311fd0f don't shrink constants down to u32 if the sign bit is set Dillon Beliveau 2023-07-22 22:05:49 -07:00
  • 5bc12895b3 fix format string Dillon Beliveau 2023-07-22 22:05:37 -07:00
  • dae333377b Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-07-22 18:22:55 -07:00
  • 38dafa90a5 Fix LL Dillon Beliveau 2023-07-22 17:04:55 -07:00
  • fe8b0a59b6 support for logging CPU state Dillon Beliveau 2023-07-15 11:55:25 -07:00
  • 75959e5f1b print constant type Dillon Beliveau 2023-07-22 17:04:08 -07:00
  • 0ce1792f34 fix JIT TLB exceptions Dillon Beliveau 2023-07-22 17:03:43 -07:00
  • 985c615249 fix count reg in matchjit interpreter Dillon Beliveau 2023-07-22 15:06:19 -07:00
  • 00c74a7329 Awful hack to fix CP0 register names in disassembly Dillon Beliveau 2023-07-22 14:50:05 -07:00
  • a0bbefa4d9 software mode in compare tool Dillon Beliveau 2023-07-22 14:02:02 -07:00
  • 56bb6d0dac check window initialization Dillon Beliveau 2023-07-16 23:38:35 -07:00
  • cf86d0d531 fix more format specifiers Dillon Beliveau 2023-07-16 22:23:45 -07:00
  • 131ae1f2c5 replace more printf format specifiers with macro Dillon Beliveau 2023-07-16 18:54:47 -07:00
  • 09263a71c7 Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-07-16 18:52:51 -07:00
  • 744d8ed655 use macros for format strings Dillon Beliveau 2023-07-16 18:45:48 -07:00
  • 7d556f46a9 add extra warning Dillon Beliveau 2023-07-16 15:48:50 -07:00
  • bc2cdc1707 fix an invalid block length bug Dillon Beliveau 2023-07-16 15:48:45 -07:00
  • f9a3fd6021 RDHWR Dillon Beliveau 2023-07-16 14:33:09 -07:00
  • 8707054bd9 tlb exceptions improvements Dillon Beliveau 2023-07-16 14:29:22 -07:00
  • b74f1f11b9 tlb exceptions, wip Dillon Beliveau 2023-07-15 15:33:24 -07:00
  • 5a1876d46a logtester verify cp0 cause and mi intr Dillon Beliveau 2023-07-15 12:49:55 -07:00
  • 22ce68e83d interrupt timing issues Dillon Beliveau 2023-07-15 12:49:45 -07:00
  • dc620ea9ef update interrupts for ip0 and ip1 Dillon Beliveau 2023-07-15 11:50:09 -07:00
  • be131d52b1 logtester updates Dillon Beliveau 2023-07-15 11:56:57 -07:00
  • c3e2cfd83b Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-07-15 09:29:35 -07:00
  • 34f70b42ac Merge branch 'dynarec_v2' of github.com:Dillonb/n64 into dynarec_v2 Dillon Beliveau 2023-07-15 09:29:05 -07:00
  • e405d343d5
         Merge 276ccf9d95 into e015f9dddf Dillon Beliveau 2023-07-13 23:54:07 +02:00
  • e015f9dddf don't latch pi for linux debug output Dillon Beliveau 2023-07-10 13:37:36 -04:00
  • b82c8b8fbe upload n64-qt.exe Dillon Beliveau 2023-07-09 15:05:56 -04:00
  • 0ad23ca84f update install-qt-action to v3 Dillon Beliveau 2023-07-09 12:42:34 -04:00
  • f2c1911776 upload n64-qt.exe microsoft-abi Dillon Beliveau 2023-07-09 15:05:56 -04:00
  • 0c6d6ae0d0 update install-qt-action to v3 Dillon Beliveau 2023-07-09 12:42:34 -04:00
  • 7c3af909ee Merge branch 'dynarec_v2' into microsoft-abi Dillon Beliveau 2023-07-09 00:20:47 -04:00
  • a925ba7e76 fix dangling pointer for compiler v1 and rsp Dillon Beliveau 2023-07-09 00:20:24 -04:00
  • c122f9df3e Windows support for dynarec v2 using the MS ABI Dillon Beliveau 2023-07-08 18:03:29 -04:00
  • a2873231a5 Add windows debug CI windows-debug-ci Dillon Beliveau 2023-07-06 23:49:28 -04:00
  • cbe1ba020c
         Change trim_gamepad_axis to return type double kev4cards 2023-06-17 22:11:26 -04:00
  • eb960e4320
         Fix various control stick issues kev4cards 2023-06-17 22:10:17 -04:00
  • 443111bd98
         Change trim_gamepad_axis to return type double kev4cards 2023-06-17 22:02:45 -04:00
  • 05e0b51ff7
         Fix various control stick issues kev4cards 2023-06-17 22:01:40 -04:00
  • 660a0dc0ff
         Add deadzone_corrected_response to device.h kev4cards 2023-06-17 21:48:57 -04:00
  • 069369f263
         Fix various control stick issues kev4cards 2023-06-17 21:46:46 -04:00
  • 5f6225453b
         Add deadzone_corrected_response to device.h kev4cards 2023-06-17 21:41:52 -04:00
  • 9fea11c536
         Fix various control stick issues kev4cards 2023-06-17 21:39:02 -04:00
  • 2f095b35d5 support spilling FGRs Dillon Beliveau 2023-06-10 16:11:53 -07:00
  • 2fed73d3c7 fix some memory errors Dillon Beliveau 2023-06-10 15:10:51 -07:00
  • fc668db02e fix unsigned divides Dillon Beliveau 2023-06-10 15:10:38 -07:00
  • d6b6927275 rewrite register flushing to be more flexible when more instructions eventually throw exceptions Dillon Beliveau 2023-06-10 15:10:30 -07:00
  • ba6b9a750d allow expiring old spill spaces Dillon Beliveau 2023-06-10 14:02:09 -07:00
  • 1c3967017f
         name deadzone and control stick variables kev4cards 2023-06-08 22:09:45 -04:00
  • 597bc316cd
         fix type issue with lenAbsolute's kev4cards 2023-06-08 18:53:19 -04:00
  • 242892c803
         Control stick fixes kev4cards 2023-06-07 21:14:03 -04:00
  • 3a51ada83f mtc0 CONFIG, DMTC0 ENTRY_LO0 & ENTRY_LO1 Dillon Beliveau 2023-06-05 22:12:39 -07:00
  • 899209351a scd, teq, tge, tgeu, tlt, tltu, tne Dillon Beliveau 2023-05-29 17:28:24 -07:00
  • 6e0caa7af1 read PRId Dillon Beliveau 2023-05-29 17:09:17 -07:00
  • 4c6eae6915 u64 and s64 multiply Dillon Beliveau 2023-05-29 17:07:54 -07:00
  • 878325ff70 correctly flush fpu registers Dillon Beliveau 2023-05-27 20:01:11 -07:00
  • 35ccca624f allow MTC0 watchlo in the jit Dillon Beliveau 2023-05-27 16:01:59 -07:00
  • e55c144fad various jit fixes Dillon Beliveau 2023-05-27 15:56:12 -07:00
  • 6d66573bad Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-05-19 17:40:02 -07:00
  • 6502f7d2f1 Fix two implicit fallthrough errors Dillon Beliveau 2023-05-18 23:16:20 -07:00
  • 44024f14f7
         Merge pull request #42 from OFFTKP/master Dillon Beliveau 2023-05-19 02:15:49 -04:00
  • 725c10e1fb Eliminate evil implicit fallthrough offtkp 2023-05-19 00:45:12 +03:00
  • 553e3d3eda better constant propagation for multiplies and divides Dillon Beliveau 2023-05-13 15:56:12 -07:00
  • 02caf5560d interrupts on the scheduler Dillon Beliveau 2023-05-13 14:29:14 -07:00
  • d7576b4379
         Merge pull request #41 from OFFTKP/master Dillon Beliveau 2023-05-03 17:03:44 -04:00
  • db288ef0cb Support reading of ADDR_VI_H_START_REG offtkp 2023-05-03 17:38:53 +03:00
  • a31d7489cc Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-04-29 14:12:01 -07:00
  • 8b9dccfdaa VI timing on scheduler Dillon Beliveau 2023-04-29 14:04:54 -07:00
  • 34d00d15f6 Merge branch 'master' into dynarec_v2 Dillon Beliveau 2023-04-29 11:16:33 -07:00
  • 41708b9350 recording demos Dillon Beliveau 2023-04-29 11:16:16 -07:00