Emulation/n64
1
0
Fork 0
mirror of https://github.com/Dillonb/n64.git synced 2025-04-02 10:42:08 -04:00
Code Issues Projects Releases Packages Wiki Activity

Commit graph

  • 814ec3550a Rename all MIPS32 stuff to just MIPS Dillon Beliveau 2020-06-17 22:05:00 -04:00
  • bff8fa082c Fixing sign extension errors Dillon Beliveau 2020-06-17 21:53:40 -04:00
  • c73ab53832 CP0 work, all instrs run with 64 bit registers Dillon Beliveau 2020-06-17 21:30:44 -04:00
  • 23f3f3febc .h files are C Dillon Beliveau 2020-06-17 17:09:16 -04:00
  • b559ff39bc Disassemble as MIPS64 Dillon Beliveau 2020-06-16 23:37:58 -04:00
  • 5a2d7f17b8 this doesn't exist Dillon Beliveau 2020-06-16 23:29:44 -04:00
  • d3103526f5 Treat as signed Dillon Beliveau 2020-06-16 23:18:13 -04:00
  • 89fc2001ed disassemble if necessary Dillon Beliveau 2020-06-16 20:16:43 -04:00
  • e720afb1cb Got basic graphics working! Dillon Beliveau 2020-06-16 20:03:26 -04:00
  • 86d229fc08 Stub V_CURRENT and rendering Dillon Beliveau 2020-06-16 17:35:45 -04:00
  • e6550af905 J instruction Dillon Beliveau 2020-06-16 17:10:13 -04:00
  • 8b2fa51e8a BGTZ, read VI Registers Dillon Beliveau 2020-06-16 00:54:32 -04:00
  • 8ef3059c61 these should be logtrace Dillon Beliveau 2020-06-16 00:42:56 -04:00
  • 8d3d689efc LB Dillon Beliveau 2020-06-16 00:39:50 -04:00
  • 0f97a7b73d Stub PIF and VI stuff Dillon Beliveau 2020-06-16 00:32:07 -04:00
  • ab2135a1cd PI status reg writes Dillon Beliveau 2020-06-15 23:20:36 -04:00
  • da97800feb Stub SI regs, ignore word writes to audio interface regs Dillon Beliveau 2020-06-15 23:15:15 -04:00
  • a19358789b Stubbing RSP Dillon Beliveau 2020-06-15 22:54:47 -04:00
  • 804b898210 Better naming Dillon Beliveau 2020-06-15 21:19:28 -04:00
  • a5cea9b366 Prefix opcode functions with mips32_ Dillon Beliveau 2020-06-15 21:14:27 -04:00
  • d4690e0ace BGEZAL Dillon Beliveau 2020-06-15 20:50:32 -04:00
  • f4c6907977 More instructions, logging changes Dillon Beliveau 2020-06-15 20:13:57 -04:00
  • 758ad31b06 Reorganize, add DMAs Dillon Beliveau 2020-06-15 18:25:26 -04:00
  • 7028e6b81a Guess it doesn't work on MacOS yet Dillon Beliveau 2020-06-15 17:40:59 -04:00
  • b85a0ab89c Missed a couple GBA -> N64 Dillon Beliveau 2020-06-15 17:37:13 -04:00
  • 13022fd044 Github actions build on Linux/MacOS Dillon Beliveau 2020-06-15 17:36:18 -04:00
  • d49e93dde7 Stub PI regs, implement the first one Dillon Beliveau 2020-06-14 17:35:23 -04:00
  • 852e15f549 Make it through the bootcode now! Dillon Beliveau 2020-06-14 16:00:58 -04:00
  • 1936990ef1 Stub cache opcode Dillon Beliveau 2020-06-14 14:32:31 -04:00
  • b11fdf25d0 Comment this out for now Dillon Beliveau 2020-06-14 13:50:02 -04:00
  • df6167e3c4 Set rd, not rt Dillon Beliveau 2020-06-14 13:49:56 -04:00
  • 5b02a53cbf JAL uses branch_abs Dillon Beliveau 2020-06-14 13:41:52 -04:00
  • cee0184d71 Register names in debug logs Dillon Beliveau 2020-06-14 13:40:36 -04:00
  • 6ea88d431f Debug log lines are green Dillon Beliveau 2020-06-14 12:24:31 -04:00
  • e7054a3a48 Fixes for logtester Dillon Beliveau 2020-06-14 12:17:28 -04:00
  • 0c4fdacc3c Simple logtester frontend Dillon Beliveau 2020-06-14 11:12:57 -04:00
  • 6b9c957424 Use a wrapper for get_register as well. Ensure all register accesses are done through wrappers Dillon Beliveau 2020-06-14 10:50:10 -04:00
  • 63dc86c566 ADD/SLT, read unused Dillon Beliveau 2020-06-13 17:39:59 -04:00
  • 8df896fb02 First REGIMM instruction: BGEZL Dillon Beliveau 2020-06-13 16:36:06 -04:00
  • cef50507f9 Stub REGIMM Dillon Beliveau 2020-06-13 16:32:30 -04:00
  • 025d693730 lots more instructions Dillon Beliveau 2020-06-13 16:21:00 -04:00
  • 534707696c Special instruction decoding Dillon Beliveau 2020-06-13 15:16:51 -04:00
  • de01b8fe76 Oops Dillon Beliveau 2020-06-11 23:12:45 -04:00
  • ab5389ac3c SB, RDRAM, bytes Dillon Beliveau 2020-06-11 23:01:42 -04:00
  • 40894b912f Finish Dillon Beliveau 2020-06-11 22:39:18 -04:00
  • b9cc24e254 Refactoring, branch delay, couple more instructions Dillon Beliveau 2020-06-11 22:36:17 -04:00
  • 7b85ca3882 SLTI Dillon Beliveau 2020-06-10 22:08:14 -04:00
  • 227cac9d9f JAL Dillon Beliveau 2020-06-10 21:56:15 -04:00
  • 4c769b6c88 More instructions, stub more hardware registers Dillon Beliveau 2020-06-10 21:15:39 -04:00
  • 8f3d6bfb39 Refactoring, implement a few more instructions Dillon Beliveau 2020-06-10 16:17:04 -04:00
  • 77a8ac60ae BNE, NOP, some debugging notes Dillon Beliveau 2020-06-10 02:58:53 -04:00
  • 8b002571e8 Stub some RDRAM interface registers Dillon Beliveau 2020-06-10 02:30:07 -04:00
  • f43d09bf69 Decode and execute a few instructions Dillon Beliveau 2020-06-10 00:54:09 -04:00
  • 847d9b51f1 Some work on decoding Dillon Beliveau 2020-06-07 17:51:09 -04:00
  • 19cfe4a199 Hook in Capstone Dillon Beliveau 2020-06-07 15:58:34 -04:00
  • 05efb5ebc7 Can read an instruction finally! Dillon Beliveau 2020-06-07 14:33:01 -04:00
  • c2dc72e94c forgot a couple files Dillon Beliveau 2020-06-07 12:40:47 -04:00
  • b87d1f4d42 Stubbing CPU Dillon Beliveau 2020-06-07 12:38:04 -04:00
  • f95e0a803c Include Dillon Beliveau 2020-06-06 18:37:36 -04:00
  • 31f9d59158 Initial commit Dillon Beliveau 2020-06-06 18:02:59 -04:00