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  • 7401ea7579 VMADH/VMADN Dillon Beliveau 2020-07-11 20:43:32 -04:00
  • 01e4426194 VMADL, VMADM, VMUDH Dillon Beliveau 2020-07-11 19:00:15 -04:00
  • afc9fa84dd RSP SBV Dillon Beliveau 2020-07-11 17:26:52 -04:00
  • 3b5a3b5634 CP1 NEG Dillon Beliveau 2020-07-11 17:22:59 -04:00
  • 4a2d4b1fbe some FPU instructions Dillon Beliveau 2020-07-11 17:14:30 -04:00
  • 596ccf8a99 RDP plugin may or may not raise an interrupt, so we should just check if it did instead of always raising one ourselves. Dillon Beliveau 2020-07-11 16:43:29 -04:00
  • d47f4bb233 Lots more RSP instructions, quiet down logging Dillon Beliveau 2020-07-11 03:41:16 -04:00
  • 77eeb620da RSP: more instructions, hook up more interfaces, unaligned reads Dillon Beliveau 2020-07-11 03:28:46 -04:00
  • 10fd9722f4 Finish up RSP interrupts, hook up RSP CP0 to more stuff Dillon Beliveau 2020-07-11 02:59:54 -04:00
  • bd30706876 RSP SUB Dillon Beliveau 2020-07-11 02:59:20 -04:00
  • 4fa2776234 RSP: SSV, reverse DMA Dillon Beliveau 2020-07-11 02:51:48 -04:00
  • 5bd0f5e9a1 Don't need to set render scale Dillon Beliveau 2020-07-11 02:41:35 -04:00
  • a74acbc850 RSP: VMACF, VMACU Dillon Beliveau 2020-07-11 02:41:17 -04:00
  • b954cccb46 Vector registers in little endian byte order Dillon Beliveau 2020-07-11 02:36:15 -04:00
  • dd7df9b1e5 RSP: CFC2, VMULF, VMULU, fix VSAR Dillon Beliveau 2020-07-11 02:24:00 -04:00
  • 5962fe68d3 uncomment Dillon Beliveau 2020-07-09 23:22:23 -04:00
  • 5d60958519 VU vec stuff, RSP SB Dillon Beliveau 2020-07-09 23:13:57 -04:00
  • 0d5b296207 RSP can only read from IMEM Dillon Beliveau 2020-07-09 22:13:55 -04:00
  • f74b0f833c Lots of CP2 stubbin' Dillon Beliveau 2020-07-09 21:30:43 -04:00
  • 8a4d6f7e4c this is better named v Dillon Beliveau 2020-07-09 19:30:15 -04:00
  • ba6e5e56eb LQV Dillon Beliveau 2020-07-09 19:26:10 -04:00
  • 00b3e66cda LDV/LSV Dillon Beliveau 2020-07-09 19:17:46 -04:00
  • 6796201a8d these decode differently Dillon Beliveau 2020-07-08 23:38:33 -04:00
  • 35f8b35a8b Stub LWC2 decodes Dillon Beliveau 2020-07-08 23:16:18 -04:00
  • 22e3a9f9a7 RSP semaphore, more RSP instructions Dillon Beliveau 2020-07-08 23:05:42 -04:00
  • f047f5b89b Angrylion working for software renderer Dillon Beliveau 2020-07-08 20:42:45 -04:00
  • 0019e0170c Save my ears a bit Dillon Beliveau 2020-07-07 21:09:11 -04:00
  • dbba52b85c Hook into more plugin stuff Dillon Beliveau 2020-07-07 21:09:03 -04:00
  • 1f7ed379dd Create OpenGL context Dillon Beliveau 2020-07-07 19:25:40 -04:00
  • 4bd2b2667f Update comments, call a hook, raise an interrupt Dillon Beliveau 2020-07-06 23:49:57 -04:00
  • 6076b4d73b Stub a ton of RDP stuff Dillon Beliveau 2020-07-06 23:39:11 -04:00
  • 01af111a7b RSP ADD, BLEZ Dillon Beliveau 2020-07-06 21:25:19 -04:00
  • a876e4d809 Load Mupen64Plus compatible RDP plugins Dillon Beliveau 2020-07-06 21:18:43 -04:00
  • 376f5ca5cd These instructions don't exist on the RSP Dillon Beliveau 2020-07-05 15:48:07 -04:00
  • 2af5431242 Tune up RSP IO, add RSP JR Dillon Beliveau 2020-07-05 15:47:33 -04:00
  • 3cf0f11277 RSP BNE, hook up first RSP CP0 register Dillon Beliveau 2020-07-05 15:02:13 -04:00
  • f1521898b3 stub RSP CP0 Dillon Beliveau 2020-07-05 14:51:10 -04:00
  • dfd60504e1 more RSP instructions Dillon Beliveau 2020-07-05 14:39:25 -04:00
  • 73fa1e7230 RSP is more separate/different than I originally thought Dillon Beliveau 2020-07-05 14:03:23 -04:00
  • 15b250ab20 Only try getting from the stream if there is data available Dillon Beliveau 2020-07-05 12:52:54 -04:00
  • 6cb307d2d8 RSP is executing instructions Dillon Beliveau 2020-07-05 12:50:42 -04:00
  • 2ec80ad5fa RSP DMA should use RSP bus Dillon Beliveau 2020-07-05 11:10:48 -04:00
  • da41969044 Pass CP0 to vatopa Dillon Beliveau 2020-07-04 17:01:00 -04:00
  • c4d05af7ea Starting to get RSP running Dillon Beliveau 2020-07-04 13:20:21 -04:00
  • 273394a24f stubbing more RSP regs Dillon Beliveau 2020-07-03 17:30:09 -04:00
  • 69108a8810 Reading AI_LENGTH Dillon Beliveau 2020-07-03 14:58:55 -04:00
  • dd1a578b82 SUB Dillon Beliveau 2020-07-03 14:55:47 -04:00
  • eb3d12d51d working on TLB stuff Dillon Beliveau 2020-07-03 14:48:28 -04:00
  • ab56575beb DDIVU, crash on divide by zero Dillon Beliveau 2020-07-03 12:44:10 -04:00
  • 9f705b050c Comment out variables that are unused (for now), DSRA32, DMULTU Dillon Beliveau 2020-07-03 12:25:02 -04:00
  • 7ebec9abcf Audio working Dillon Beliveau 2020-07-03 11:59:15 -04:00
  • b045df331c Fix LWL/LWR instructions. Several small tweaks. Input should work now Dillon Beliveau 2020-07-02 23:08:01 -04:00
  • e9c177523b print message when passing testcase Dillon Beliveau 2020-06-30 20:21:56 -04:00
  • edfd4dc335 Include stripped-down versions of the CPU tests Dillon Beliveau 2020-06-30 20:05:35 -04:00
  • f6154f1cc5 CPU tests are file based Dillon Beliveau 2020-06-29 23:15:45 -04:00
  • 5137e8772a More tests Dillon Beliveau 2020-06-28 12:25:13 -04:00
  • f759441c00 Start stubbing tests Dillon Beliveau 2020-06-28 12:04:03 -04:00
  • 1a4a8b9ce3 DSLLV Dillon Beliveau 2020-06-27 22:54:03 -04:00
  • 42a62c8085 Controller/PIF tweaking/flailing Dillon Beliveau 2020-06-27 22:13:11 -04:00
  • 0ae1f77b50 more buttons, pif improvements. controllers still broken Dillon Beliveau 2020-06-27 18:59:24 -04:00
  • 103e85bc68 c_sub Dillon Beliveau 2020-06-27 13:34:01 -04:00
  • 06e8cd0d3f c_lt Dillon Beliveau 2020-06-27 13:26:11 -04:00
  • 75a0a7fbb0 Fix controllers Dillon Beliveau 2020-06-27 13:26:03 -04:00
  • 01faefa1d4 Remove mock controller data Dillon Beliveau 2020-06-27 11:19:23 -04:00
  • 055c2829d1 Fix 16 bit graphics. Begin implementing controllers Dillon Beliveau 2020-06-27 01:22:34 -04:00
  • ff4df4fb22 Fix DMA Dillon Beliveau 2020-06-25 00:45:05 -04:00
  • c2516ed8cf Mock controller Dillon Beliveau 2020-06-25 00:44:09 -04:00
  • ddd09844d0 Fix bugs, add instructions, add restrictions to CP0 writes Dillon Beliveau 2020-06-25 00:42:40 -04:00
  • b1f1810003 Fix sign extension bug Dillon Beliveau 2020-06-24 21:31:38 -04:00
  • 920cb73080 Fix SH Dillon Beliveau 2020-06-24 00:45:20 -04:00
  • 1fad26a879 Mock audio, lotsa tweaks Dillon Beliveau 2020-06-24 00:20:57 -04:00
  • 3ab4224fb6 Quieter logs Dillon Beliveau 2020-06-24 00:15:29 -04:00
  • 6fc41e98ed Interrupt logging, DP interrupt Dillon Beliveau 2020-06-23 22:22:39 -04:00
  • e8db7847cb Automatically adjust texture width Dillon Beliveau 2020-06-23 22:22:29 -04:00
  • 6147a9b0d9 use wrapper method Dillon Beliveau 2020-06-23 22:20:23 -04:00
  • 8d24c34f1b less messy Dillon Beliveau 2020-06-23 22:20:12 -04:00
  • 106800e23e Fix LWL/LWR/SWL/SWR Dillon Beliveau 2020-06-23 22:19:50 -04:00
  • 5800fa4b73 BLTZ, BLTZL, MOV.S, MOV.D, JALR Dillon Beliveau 2020-06-22 21:00:36 -04:00
  • 50882d8f8d LWU, fix interrupts, mock AI status reg Dillon Beliveau 2020-06-22 20:44:07 -04:00
  • 4b4e8e8f5c Fix sign extension Dillon Beliveau 2020-06-22 18:59:27 -04:00
  • f4377266fb each instruction takes two cycles Dillon Beliveau 2020-06-22 18:41:01 -04:00
  • 115f7646c3 interrupt tweaks Dillon Beliveau 2020-06-22 18:34:34 -04:00
  • 96960cf16e Make RDRAM 8MB Dillon Beliveau 2020-06-21 22:43:51 -04:00
  • 882f1cfcb7 Fix TRUNC, fix printf tokens Dillon Beliveau 2020-06-21 15:01:13 -04:00
  • b42f4aca15 <Good commit message> Dillon Beliveau 2020-06-21 05:33:39 -04:00
  • c53b3d6f12 Stub out args for float instructions too Dillon Beliveau 2020-06-21 03:01:20 -04:00
  • a467eb0ded more FPU stubbin, C_LE, BC1T, BC1F Dillon Beliveau 2020-06-21 03:00:08 -04:00
  • dd61f34401 Oops Dillon Beliveau 2020-06-21 02:42:41 -04:00
  • 308695f4c5 Instruction decoding fixes, FPU stuff Dillon Beliveau 2020-06-21 02:42:03 -04:00
  • 89d2a7a642 interrupts, exceptions, more instructions, logtester initializes registers to ares' values, etc etc Dillon Beliveau 2020-06-21 00:07:59 -04:00
  • e2e3b0fd3f First floating point opcodes: mul.s and mul.d Dillon Beliveau 2020-06-20 00:29:57 -04:00
  • a4b92a03c2 More instructions, probably broken exception handling, floating point stuff Dillon Beliveau 2020-06-18 22:18:58 -04:00
  • ddc0dc2cdb SH, SRA, 16 bit reads/writes Dillon Beliveau 2020-06-18 20:25:43 -04:00
  • 9b7c8406db New instructions, bug fixes, allowing access to more registers Dillon Beliveau 2020-06-18 20:02:15 -04:00
  • 6c0131390c CFC1, CTC1 Dillon Beliveau 2020-06-18 00:49:12 -04:00
  • 0c941f8754 Redo how CP0 registers are stored, implement status register Dillon Beliveau 2020-06-17 23:46:42 -04:00
  • 8c16c4fe05 Fix coprocessor instruction decoding. MFC0 instruction implemented Dillon Beliveau 2020-06-17 23:23:57 -04:00
  • ea896e7975 Doubleword adds Dillon Beliveau 2020-06-17 23:00:00 -04:00
  • 1d5b6d4da3 Show disassembly in level-2 decode functions too Dillon Beliveau 2020-06-17 22:38:11 -04:00
  • 5e76ba9e91 Load and store doublewords Dillon Beliveau 2020-06-17 22:27:58 -04:00