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  • a822b0ff97 use mold linker if found Dillon Beliveau 2024-07-07 20:50:12 -07:00
  • 1e35bc2824 set C standard to 11, remove uses of atomic_load and atomic_store Dillon Beliveau 2024-07-07 20:50:01 -07:00
  • 2b198e3992 ignore writes to MI_INTR_REG Dillon Beliveau 2024-06-24 23:50:22 -07:00
  • ed09657d8b fix logfatal Dillon Beliveau 2024-06-24 21:17:14 -07:00
  • a002d7756b cleanup disassemble.cpp a bit Dillon Beliveau 2024-06-16 15:13:46 -07:00
  • ad5924d02b update and fix shell.nix for NixOS 24.05 and LLVM 18 Dillon Beliveau 2024-06-02 12:46:33 -07:00
  • b7b2a12f32 Remove pkgs.hello Dillon Beliveau 2024-05-13 23:18:47 -07:00
  • b40a30f6ff Fix all remaining warnings on clang 17 Dillon Beliveau 2024-05-13 23:09:17 -07:00
  • 03d655ff6c better ABI compliance Dillon Beliveau 2024-05-12 17:07:07 -07:00
  • 2e9e0bd744 refactor block lookup to be more flexible Dillon Beliveau 2024-05-12 16:58:51 -07:00
  • 55939a662d write perf map file on linux Dillon Beliveau 2024-05-09 21:13:31 -07:00
  • 08ec8b6eb5 add glibc headers to CPATH, suppress including mainfile in preamble clangd warning Dillon Beliveau 2024-05-09 21:06:10 -07:00
  • 7dc0777a8d add vulkan loader to LD_LIBRARY_PATH Dillon Beliveau 2024-05-09 20:43:36 -07:00
  • 6e40a93ea1 add direnv config and shell.nix Dillon Beliveau 2024-05-09 20:40:08 -07:00
  • 1e461dc014 implement data cache Dillon Beliveau 2024-04-14 16:12:15 -07:00
  • 4a727909bd remove junk print statements Dillon Beliveau 2024-04-13 21:18:13 -07:00
  • 2e8feaff18 fix case labels Dillon Beliveau 2024-04-13 20:57:24 -07:00
  • 5e785b09c3 implement icache Dillon Beliveau 2024-04-13 18:03:41 -07:00
  • 393d9c9ca6 cleanup Dillon Beliveau 2024-04-13 18:02:45 -07:00
  • 24776897ea resolving a virtual address also returns whether it's cached Dillon Beliveau 2024-04-13 14:22:53 -07:00
  • d69b075524 remove unused and unimplemented prototype Dillon Beliveau 2024-04-13 13:43:47 -07:00
  • cc934dfb9b Merge branch 'master' into rsp_dynarec_v2 rsp_dynarec_v2 Dillon Beliveau 2024-02-24 18:55:24 -08:00
  • bfcf63989e fix formatting Dillon Beliveau 2024-02-24 18:53:55 -08:00
  • 7e948b8217
         Merge pull request #49 from xkevio/patch-1 Dillon Beliveau 2024-02-24 18:52:12 -08:00
  • 4ed6ae72d2
         fix: pack -> pak Kevin K 2024-02-25 03:49:32 +01:00
  • 6f651209d4 add include Dillon Beliveau 2023-12-28 17:05:57 +01:00
  • 9181f5445c Remove SCHEDULER_HANDLE_INTERRUPT event before queueing a new one Dillon Beliveau 2023-10-18 00:55:17 -07:00
  • f570771e57 stub vmulf and ir instruction to get VTE Dillon Beliveau 2023-09-24 12:51:05 -07:00
  • 8d0f140e0f fix IR_VPR_INSERT Dillon Beliveau 2023-09-17 23:00:10 -07:00
  • 1ecbe0b3ad stub CP2, new IR instruction for inserting into the middle of a VPR, WIP MTC2 Dillon Beliveau 2023-09-17 20:09:06 -07:00
  • 43b38f7950 oops Dillon Beliveau 2023-09-16 18:55:01 -07:00
  • 82e19a9bf4 WIP SDV Dillon Beliveau 2023-09-16 13:03:26 -07:00
  • 0c8214ed63 oops Dillon Beliveau 2023-09-12 20:39:03 -07:00
  • 881f63fca6 remove an instruction Dillon Beliveau 2023-09-12 20:07:17 -07:00
  • 4c83d62e68 fix LDV Dillon Beliveau 2023-09-11 22:42:56 -07:00
  • d3a2b5ee79 add missing calls to reset_temp_vpr Dillon Beliveau 2023-09-11 22:21:00 -07:00
  • c5c962be33 refactor common code, implement lbv and lsv Dillon Beliveau 2023-09-11 22:19:13 -07:00
  • e6c0d04a80 finish stubbing remaining bector loads Dillon Beliveau 2023-09-11 21:23:24 -07:00
  • 3a5a85dd81 set code mask correctly Dillon Beliveau 2023-09-11 21:17:03 -07:00
  • bbe5cf3b42 stub remaining vector loads Dillon Beliveau 2023-09-11 01:22:58 -07:00
  • 533d188afb stub remaining vector stores Dillon Beliveau 2023-09-11 01:15:12 -07:00
  • 0ff381b936 use macros Dillon Beliveau 2023-09-11 00:53:46 -07:00
  • 83fda35a84 fix macro Dillon Beliveau 2023-09-11 00:46:42 -07:00
  • b954a31af4 sqv Dillon Beliveau 2023-09-10 23:04:30 -07:00
  • d27bd3ff9a add a monster comment Dillon Beliveau 2023-09-10 21:48:55 -07:00
  • 2fdd688a41 shrink regs used Dillon Beliveau 2023-09-10 21:26:45 -07:00
  • 65b0dbfe5d finish LQV Dillon Beliveau 2023-09-10 21:24:16 -07:00
  • 0d9f1fb154 remove commented code Dillon Beliveau 2023-09-10 16:42:24 -07:00
  • 984f739f77 improve LQV, fix disassembly of LWC2/SWC2 Dillon Beliveau 2023-09-10 15:42:56 -07:00
  • de83d0e5bd wip SDV, work LDV and LQV Dillon Beliveau 2023-09-09 17:38:12 -07:00
  • f5297ca9ad lqv Dillon Beliveau 2023-09-08 20:40:41 -07:00
  • 6960103bad flush VPRs, implement LDV probably incorrectly Dillon Beliveau 2023-09-08 19:48:43 -07:00
  • 1de96772fe WIP LDV, stub LQV Dillon Beliveau 2023-09-07 23:49:22 -07:00
  • 0f713d0968 bypass capstone for unique RSP instructions Dillon Beliveau 2023-09-07 23:44:04 -07:00
  • b2f9f05cbd stub SDV Dillon Beliveau 2023-09-07 21:32:24 -07:00
  • ed66071bac stub LDV Dillon Beliveau 2023-09-07 20:44:16 -07:00
  • ff0710cc08 stub vector register type Dillon Beliveau 2023-09-07 19:55:38 -07:00
  • 0fcf59b5a1 some more stubbing Dillon Beliveau 2023-09-05 00:15:27 -07:00
  • 2155afa2f2 Merge branch 'master' into rsp_dynarec_v2 Dillon Beliveau 2023-09-04 21:59:58 -07:00
  • 42e5ad9887 Fix RSP tests Dillon Beliveau 2023-09-04 21:59:45 -07:00
  • ba8aaa8e78 better RSP loads Dillon Beliveau 2023-09-04 20:21:56 -07:00
  • 7ddcb58756 implement RSP break Dillon Beliveau 2023-09-04 18:06:27 -07:00
  • c8caf7a25c Merge branch 'master' into rsp_dynarec_v2 Dillon Beliveau 2023-09-04 16:55:58 -07:00
  • cf9a1bde4a switch DMEM back to big endian Dillon Beliveau 2023-09-04 16:55:45 -07:00
  • 0c5d994456 more RSP instructions, stub out vector load/stores Dillon Beliveau 2023-09-04 15:56:09 -07:00
  • 1bbdf188f0 correct memory loads for RSP Dillon Beliveau 2023-09-04 13:04:10 -07:00
  • 60a6d95b46 implement more RSP instructions in JIT, stub out a bunch more Dillon Beliveau 2023-09-04 12:49:16 -07:00
  • 7b1958a92f fix COP0 register names for the RSP Dillon Beliveau 2023-09-04 01:57:22 -07:00
  • fc979a6fb9 RSP JIT: beq, lw, andi Dillon Beliveau 2023-09-04 01:41:36 -07:00
  • 6020e5af3f RSP run_block function, make JIT more generic and support RSP better, ADDI in RSP JIT Dillon Beliveau 2023-09-04 01:00:58 -07:00
  • 43ddd315d0 rsp J opcode, compile RSP register loads correctly Dillon Beliveau 2023-09-03 12:02:05 -07:00
  • 3873e7b5ac start migrating RSP JIT to v2 recompiler Dillon Beliveau 2023-09-02 11:34:34 -07:00
  • 737c9b05a6 optimize slightly Dillon Beliveau 2023-08-29 23:36:35 -07:00
  • 70f467421b vectorize RSP code cache checking Dillon Beliveau 2023-08-29 20:50:29 -07:00
  • 012b1c9d40 RSP codecache rework to reduce thrashing Dillon Beliveau 2023-08-29 01:13:36 -07:00
  • bdc075a8a3 common path for setting cp0 status reg for both 32 and 64 bit sizes Dillon Beliveau 2023-08-28 23:43:33 -07:00
  • b96f176cb3 replace magic number Dillon Beliveau 2023-08-28 23:36:40 -07:00
  • f9543f3cdf remove bad checks now that the PI bus is handled Dillon Beliveau 2023-08-28 21:40:05 -07:00
  • d15e893ce3 fix comment Dillon Beliveau 2023-08-28 21:37:58 -07:00
  • 2edf1d669a Handle PI bus more completely. Fixes Paper Mario. Dillon Beliveau 2023-08-28 21:27:30 -07:00
  • 9acfc0b68c only build dynarec_compare if dynarec is enabled Dillon Beliveau 2023-08-28 00:10:12 -07:00
  • 91c198fe60 support fully disabling dynarec Dillon Beliveau 2023-08-27 23:46:50 -07:00
  • 9f1e3f0df7 Allow building without dynarec v1 Dillon Beliveau 2023-08-27 23:21:01 -07:00
  • 72252bcff0 move v2_compiler_x64.c to a platform specific section Dillon Beliveau 2023-08-27 22:19:04 -07:00
  • 70a48ef315 move platform specific JIT code to platform specific file Dillon Beliveau 2023-08-27 22:08:14 -07:00
  • b831c8e8e9 include failure message in the crash dump Dillon Beliveau 2023-08-27 21:00:13 -07:00
  • 3c43811109 Automatically regenerate version.h if the git commit hash changes Dillon Beliveau 2023-08-27 20:51:11 -07:00
  • ca9585b526 Support for saving crash dumps Dillon Beliveau 2023-08-27 20:40:51 -07:00
  • 06dd84da3f implement c_nge and c_ngt in jit Dillon Beliveau 2023-08-27 14:47:24 -07:00
  • a3e4b3c77e remove some FGR size checks Dillon Beliveau 2023-08-27 13:20:11 -07:00
  • a271682719 rename N64_USE_SIMD directive to N64_HAVE_SSE Dillon Beliveau 2023-08-27 13:10:55 -07:00
  • 182b7e2b92 Fix build on Linux Dillon Beliveau 2023-08-26 23:17:18 -07:00
  • f08c2ee007 Cache TLB resolutions Dillon Beliveau 2023-08-26 18:17:29 -07:00
  • 390beaf4d7 swap a function pointer for virtual address resolution when changing modes Dillon Beliveau 2023-08-26 12:51:48 -07:00
  • 53ceffaaa3 fix unused variable warning when N64_LOG_COMPILATIONS is not defined Dillon Beliveau 2023-08-25 23:44:15 -07:00
  • e30194a2bc detect idle loops with J self; nop Dillon Beliveau 2023-08-25 22:06:56 -07:00
  • 2b91032156 remove defunct gamepad trim test Dillon Beliveau 2023-08-25 20:46:38 -07:00
  • 53bb7f4863
         Merge pull request #48 from kev4cards/control-stick-change Dillon Beliveau 2023-08-25 20:45:21 -07:00
  • e9154acc5e
         Change control stick approach kev4cards 2023-08-25 23:32:16 -04:00
  • d16a934c58 enable idle loop detection by default Dillon Beliveau 2023-08-25 20:30:18 -07:00