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  • 6483d0f9b4 adjust RSP test output Dillon Beliveau 2020-08-01 19:23:56 -04:00
  • 901683b383 Fix LDV/SDV Dillon Beliveau 2020-08-01 18:55:33 -04:00
  • 68e73ee2fc fix LUV Dillon Beliveau 2020-08-01 18:18:13 -04:00
  • 7916c3888e uncomment all tests Dillon Beliveau 2020-08-01 15:45:10 -04:00
  • a6d9f447aa don't fail tests on unimplemented RSP instructions Dillon Beliveau 2020-08-01 15:43:23 -04:00
  • 5909e36aeb VRSQH/VRSQL Dillon Beliveau 2020-08-01 15:43:05 -04:00
  • 16f4b8ebc4 vaddc Dillon Beliveau 2020-08-01 15:42:51 -04:00
  • 6ac1a3f872 LTV/STV Dillon Beliveau 2020-08-01 15:42:34 -04:00
  • 480defd022 mips:4000 in gdb Dillon Beliveau 2020-08-01 15:42:16 -04:00
  • bf15110bd9 cleanup print statements all over tlb code, implement some RSP stuff Dillon Beliveau 2020-07-30 21:10:42 -04:00
  • 58fe7f5876 fix TLB Dillon Beliveau 2020-07-28 23:03:53 -04:00
  • 6f66a5ee07 don't debug gdbstub Dillon Beliveau 2020-07-28 23:03:06 -04:00
  • 72e8726cf9 don't do debugger stuff if -d isn't passed Dillon Beliveau 2020-07-28 23:02:44 -04:00
  • cd11d7f113 cleanup message Dillon Beliveau 2020-07-26 23:46:57 -04:00
  • 10a9044e90 endianness, again Dillon Beliveau 2020-07-26 23:22:04 -04:00
  • 155409cd0a
         Merge pull request #1 from Dillonb/tlb-wip Dillon Beliveau 2020-07-26 23:20:33 -04:00
  • 1f31691f97
         Merge pull request #2 from Dillonb/gdb-stub Dillon Beliveau 2020-07-26 22:31:06 -04:00
  • 1f5779e09b breakpoints, -d option, beginnings of a memory map, endianness Dillon Beliveau 2020-07-26 17:51:30 -04:00
  • b87c479a67 step fixes, endianness fixes Dillon Beliveau 2020-07-26 12:38:44 -04:00
  • 114e4c48c8 Initial sorta-working gdb stub Dillon Beliveau 2020-07-25 21:44:49 -04:00
  • 8c5a150409 not a fatal error, just log it Dillon Beliveau 2020-07-24 19:53:35 -04:00
  • f60bb78993 typo Dillon Beliveau 2020-07-24 19:52:02 -04:00
  • d2ee10bfb3 tlb fixes, odd pages Dillon Beliveau 2020-07-24 10:44:06 -04:00
  • 24a35468cf get sockets set up for gdb stub Dillon Beliveau 2020-07-24 08:46:00 -04:00
  • 6265cda32c handle pagemask correctly Dillon Beliveau 2020-07-23 21:44:16 -04:00
  • a6a9115a31 Merge branch 'master' into tlb-wip Dillon Beliveau 2020-07-23 01:08:17 -04:00
  • 3b05af35d2 Cleanup print statements Dillon Beliveau 2020-07-23 01:07:28 -04:00
  • 6ac1fdee01 DDIV / DADDIU Dillon Beliveau 2020-07-23 01:07:11 -04:00
  • b3d709c464 remove check Dillon Beliveau 2020-07-23 00:45:04 -04:00
  • 4a2b259645 sync RSP to CPU at correct ratio Dillon Beliveau 2020-07-23 00:44:57 -04:00
  • 4bae06422a Rework DMA Dillon Beliveau 2020-07-23 00:43:56 -04:00
  • a289063b97 fix LDV Dillon Beliveau 2020-07-23 00:33:17 -04:00
  • 68ec7e0525 Fix MTC2 Dillon Beliveau 2020-07-23 00:30:48 -04:00
  • c2fc742975 MFC2 Dillon Beliveau 2020-07-23 00:29:31 -04:00
  • d090bef4d8 LRV Dillon Beliveau 2020-07-23 00:29:04 -04:00
  • 3e5545b1e9 RSP SRLV Dillon Beliveau 2020-07-23 00:17:15 -04:00
  • 4cd1a78c89 fix offsets Dillon Beliveau 2020-07-23 00:15:02 -04:00
  • 5f9b169f7c mupen64plus cpu comparison mupen-compare Dillon Beliveau 2020-07-22 19:18:25 -04:00
  • 0451fd418b crash when RSP PC misaligned Dillon Beliveau 2020-07-21 22:18:59 -04:00
  • 3d6379b258 fix VMUDH Dillon Beliveau 2020-07-20 19:02:22 -04:00
  • 65c56cec4a pass VMADM Dillon Beliveau 2020-07-20 18:54:29 -04:00
  • 40098f5d0f use correct settings Dillon Beliveau 2020-07-20 18:44:16 -04:00
  • a0f98083f1 fix log line Dillon Beliveau 2020-07-19 17:49:57 -04:00
  • e1fcd6e9a1 fix VRCPH Dillon Beliveau 2020-07-19 17:49:05 -04:00
  • a25106e31d fix VADD Dillon Beliveau 2020-07-19 17:48:53 -04:00
  • f20cd11f3a fix VRCPL Dillon Beliveau 2020-07-19 16:45:44 -04:00
  • d00a2d8e63 fix VLT Dillon Beliveau 2020-07-19 16:07:48 -04:00
  • 5cb8642580 VXOR/VNXOR set the acc as well Dillon Beliveau 2020-07-19 16:00:27 -04:00
  • 6ec013a332 rewrite VCH Dillon Beliveau 2020-07-19 15:53:29 -04:00
  • c471fc0568 dumb typo Dillon Beliveau 2020-07-19 15:40:26 -04:00
  • 1976f74588 remove pseudocode comments Dillon Beliveau 2020-07-19 14:20:59 -04:00
  • 0f7ab14192 free(system) Dillon Beliveau 2020-07-19 14:19:10 -04:00
  • cbf8bdf7b4 Fixing VCL Dillon Beliveau 2020-07-19 14:19:02 -04:00
  • 4df35426a7 endianness strikes again Dillon Beliveau 2020-07-19 14:17:57 -04:00
  • 103d15811a VOR and VNOR set the accumulator too Dillon Beliveau 2020-07-19 13:33:17 -04:00
  • 36a3a3c380 VAND and VNAND set the accumulator too Dillon Beliveau 2020-07-19 13:10:44 -04:00
  • a7fe26cc38 couple more (probably broken) RSP instructions Dillon Beliveau 2020-07-19 13:02:07 -04:00
  • 647b541a1f VRCPH Dillon Beliveau 2020-07-19 10:49:04 -04:00
  • 80434c5fde VMUDL Dillon Beliveau 2020-07-18 20:18:41 -04:00
  • 9911d9637b VCL Dillon Beliveau 2020-07-18 20:11:27 -04:00
  • 4c493edc34 VCH Dillon Beliveau 2020-07-18 20:11:19 -04:00
  • b1adb985e0 VADD Dillon Beliveau 2020-07-18 20:11:05 -04:00
  • fda27a3459 fix RSP registers Dillon Beliveau 2020-07-18 20:10:55 -04:00
  • 4ab59dcb71 this passes now Dillon Beliveau 2020-07-17 23:11:01 -04:00
  • ac772772a6 Don't clear RSP state in between subtest runs Dillon Beliveau 2020-07-17 23:07:20 -04:00
  • b369d71ff0 these now pass Dillon Beliveau 2020-07-17 00:37:53 -04:00
  • 46c4ded4ca use correct element Dillon Beliveau 2020-07-17 00:34:30 -04:00
  • 82d4b279bf Fix VMUDH Dillon Beliveau 2020-07-16 21:27:52 -04:00
  • 1d2af6cf20 comment out tests that don't pass yet Dillon Beliveau 2020-07-15 21:21:18 -04:00
  • 1ea21db31e Remove this kinda useless line Dillon Beliveau 2020-07-13 20:25:11 -04:00
  • 697ed11f35
         Update README.md Dillon Beliveau 2020-07-15 14:13:23 -04:00
  • 77a1f081d0
         Update README.md Dillon Beliveau 2020-07-15 14:01:02 -04:00
  • 70ab74ff85
         Create README.md Dillon Beliveau 2020-07-15 13:59:09 -04:00
  • ddedacea6f RSP halfword unaligned writes Dillon Beliveau 2020-07-12 23:28:45 -04:00
  • d96928ec71 check element == 0. will need to get implemented later Dillon Beliveau 2020-07-12 23:26:36 -04:00
  • d3dbabb9bb LLV Dillon Beliveau 2020-07-12 23:00:24 -04:00
  • ad18db7b1d VMUDM/VMUDN Dillon Beliveau 2020-07-12 23:00:16 -04:00
  • 2a2de4ca4d LSV Dillon Beliveau 2020-07-12 23:00:03 -04:00
  • 8afd5e8047 ADDU and ADDIU are just ADD and ADDI in the RSP Dillon Beliveau 2020-07-12 22:47:56 -04:00
  • c46d43f5d3 Make the text output nicer Dillon Beliveau 2020-07-12 22:43:55 -04:00
  • 716487e001 Housekeeping Dillon Beliveau 2020-07-12 22:05:42 -04:00
  • 21ef0712a9 fix SQV Dillon Beliveau 2020-07-12 22:02:13 -04:00
  • 2f9416b0f1 Display expected/actual test output Dillon Beliveau 2020-07-12 22:00:36 -04:00
  • f5921e18d4 Still not perfect, but improve LQV and SQV Dillon Beliveau 2020-07-12 21:48:17 -04:00
  • fde4ab30e2 This should be a 32 bit conversion Dillon Beliveau 2020-07-12 21:44:41 -04:00
  • 4cd1827209 TLB WIP Dillon Beliveau 2020-07-12 18:03:27 -04:00
  • d098b80806 RSP unaligned word reads Dillon Beliveau 2020-07-12 17:48:58 -04:00
  • 4a3ec2c185 VAND, VNAND, VNOR, VNXOR, VOR, VXOR Dillon Beliveau 2020-07-12 17:48:37 -04:00
  • 51f9064f3f Improve LQV and SQV, not perfect yet though Dillon Beliveau 2020-07-12 17:47:53 -04:00
  • 249b14b849 no need to mask twice Dillon Beliveau 2020-07-12 17:42:31 -04:00
  • 7d53611e9f Convert expected value to little endian Dillon Beliveau 2020-07-12 17:32:33 -04:00
  • 74bf20656c Fix unaligned word writes Dillon Beliveau 2020-07-12 17:31:23 -04:00
  • c6206d14b4 check test output Dillon Beliveau 2020-07-12 16:29:54 -04:00
  • bc690f1e2e RSP LUI Dillon Beliveau 2020-07-12 16:05:04 -04:00
  • 64b36ecb2b RSP tests with autogenerated CMake configs and input data Dillon Beliveau 2020-07-12 15:46:58 -04:00
  • 6c6f5b2780 Add testcases for RSP Dillon Beliveau 2020-07-12 14:36:42 -04:00
  • 9031d91ae0 CPU test cases in cpu subdir Dillon Beliveau 2020-07-12 12:52:41 -04:00
  • f50aededc6 Fix VSAR Dillon Beliveau 2020-07-12 12:06:55 -04:00
  • 9dc8409c96 Check RDP interrupts from the callback only Dillon Beliveau 2020-07-11 23:49:00 -04:00
  • ca0a80d163 RSP unaligned word writes Dillon Beliveau 2020-07-11 20:43:52 -04:00