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  • c470d20694 closer on the VRCP family of instructions, not quite there yet Dillon Beliveau 2020-09-19 21:21:43 -04:00
  • 079e046d41 get_vte takes a pointer Dillon Beliveau 2020-09-19 20:40:44 -04:00
  • bab25d5ffa rewrite VCH Dillon Beliveau 2020-09-19 20:31:18 -04:00
  • d73ecf01de fix LTE compare in VCL Dillon Beliveau 2020-09-19 20:10:03 -04:00
  • 5acc66a105 hacky hack, but don't run the RSP for a second step if it's halted Dillon Beliveau 2020-09-19 14:49:56 -04:00
  • 3c5af03124 fix VCR Dillon Beliveau 2020-09-13 16:31:29 -04:00
  • db8ce9e6c3 fix VCL Dillon Beliveau 2020-09-13 13:46:18 -04:00
  • 7449bebf55 fix VNE Dillon Beliveau 2020-09-13 13:26:51 -04:00
  • 6159fa9a0f fix VMOV Dillon Beliveau 2020-09-13 13:04:27 -04:00
  • 0312bf80c2 set vco.h to zero in VCR Dillon Beliveau 2020-09-13 12:16:49 -04:00
  • e4e49cef01 split up vsvtvd macro Dillon Beliveau 2020-09-13 11:54:57 -04:00
  • 0b889cda77 NOR in a slightly better spot Dillon Beliveau 2020-09-12 19:17:30 -04:00
  • c1dfea1716 RSP JALR and NOR Dillon Beliveau 2020-09-12 17:42:33 -04:00
  • db58f828d2 add -march=native to compile flags. Dillon Beliveau 2020-09-12 17:29:38 -04:00
  • 9f043ded4b fairly broken VCR Dillon Beliveau 2020-09-12 17:29:25 -04:00
  • f4351b5146 no e!=0 check in vrsql Dillon Beliveau 2020-09-12 15:11:32 -04:00
  • 7537f5e098 VADDC lane selection Dillon Beliveau 2020-09-12 15:11:21 -04:00
  • 1fa7f8dded VABS Dillon Beliveau 2020-09-12 14:48:01 -04:00
  • c6baa1a83e lane selection in VSUB and VSUBC Dillon Beliveau 2020-09-12 14:42:14 -04:00
  • a5a44572ea lane selection in VAND Dillon Beliveau 2020-09-12 14:11:51 -04:00
  • d3aa85ed79 too excited here again Dillon Beliveau 2020-09-12 14:11:09 -04:00
  • eaffb22e39 VMOV Dillon Beliveau 2020-09-12 14:10:58 -04:00
  • 9f2b2eaedb lane selection vmrg Dillon Beliveau 2020-09-12 14:04:34 -04:00
  • 625c36b955 lane selection in vmrg Dillon Beliveau 2020-09-12 14:04:03 -04:00
  • 6365e28f5a lane selection in vge Dillon Beliveau 2020-09-12 14:01:01 -04:00
  • b0baf406f8 got a little too excited with these Dillon Beliveau 2020-09-12 13:59:50 -04:00
  • 30ddd2d579 handle element in VADD Dillon Beliveau 2020-09-12 13:56:07 -04:00
  • b395a39224 handle element in VCH Dillon Beliveau 2020-09-12 13:55:11 -04:00
  • f7244af6f0 remove some element != 0 checks where handled Dillon Beliveau 2020-09-12 13:55:01 -04:00
  • 92c6559472 add element != 0 checks everywhere Dillon Beliveau 2020-09-12 13:51:34 -04:00
  • cae62af7a0 vte in VNXOR Dillon Beliveau 2020-09-12 13:46:33 -04:00
  • 36475bc68f VNE Dillon Beliveau 2020-09-12 13:46:20 -04:00
  • f9ee9952d6 VEQ Dillon Beliveau 2020-09-12 13:39:22 -04:00
  • d3df05f0f0 vte-related macros Dillon Beliveau 2020-09-12 13:39:15 -04:00
  • 9354545c5c rsp XORI Dillon Beliveau 2020-09-12 13:18:05 -04:00
  • 62ecc3318d use VTE in VCL Dillon Beliveau 2020-09-12 13:17:38 -04:00
  • 192ae48fc4 unimplemented macro requires semicolon Dillon Beliveau 2020-09-12 13:06:28 -04:00
  • a0e235adbc fix STV Dillon Beliveau 2020-09-12 09:36:51 -04:00
  • 0e0a89b520 cleanup RSP test output Dillon Beliveau 2020-09-12 08:48:26 -04:00
  • 8dabc969e2 fix LTV Dillon Beliveau 2020-09-12 08:48:17 -04:00
  • 15d4026774 fix VMACU Dillon Beliveau 2020-09-07 20:47:59 -04:00
  • 06b9e5a810 VMULQ check for zero element Dillon Beliveau 2020-09-07 20:39:04 -04:00
  • d952071807 fix VMULU Dillon Beliveau 2020-09-07 20:38:42 -04:00
  • f1d90f31e3 fix several multiplies Dillon Beliveau 2020-09-07 20:31:09 -04:00
  • 5282675cac fix VMACF Dillon Beliveau 2020-09-07 19:34:44 -04:00
  • e85f6303f7 fix VMULF Dillon Beliveau 2020-09-07 19:33:21 -04:00
  • f144a83a01 element selector in multiplies Dillon Beliveau 2020-09-07 19:04:12 -04:00
  • 531be9d51c fix clamping in VMADN Dillon Beliveau 2020-09-07 16:02:30 -04:00
  • 10a5bfde7f Merge branch 'master' of github.com:Dillonb/n64 into master Dillon Beliveau 2020-09-07 14:55:16 -04:00
  • 74afbafe25 all log macros need semicolons Dillon Beliveau 2020-09-07 14:05:45 -04:00
  • 78aa785093 rsp tests display all log differences before exiting Dillon Beliveau 2020-09-06 11:09:04 -04:00
  • 5464d9e027 same fix for vrcp Dillon Beliveau 2020-09-05 16:18:38 -04:00
  • 0b487d69c9 fix issues with vrsq Dillon Beliveau 2020-09-05 16:03:23 -04:00
  • 09d28dd703 fix typo in rsq as well Dillon Beliveau 2020-09-05 15:41:47 -04:00
  • 56f7ce393d vrcp doesn't unload divin, apparently Dillon Beliveau 2020-09-05 15:41:20 -04:00
  • 560440f0ae should be 0x10000 Dillon Beliveau 2020-09-05 15:34:57 -04:00
  • c0d9b959ba Check logs of all RSP tests Dillon Beliveau 2020-09-04 23:56:48 -04:00
  • 59222226ae broken lfv Dillon Beliveau 2020-08-17 22:18:39 -04:00
  • d145941983 move sign extensions in RSP load/stores to common function Dillon Beliveau 2020-08-17 12:17:43 -04:00
  • e51ecf2970 fix SHV some more Dillon Beliveau 2020-08-17 11:45:38 -04:00
  • b3a8291a3b fix LHV some more Dillon Beliveau 2020-08-17 11:29:07 -04:00
  • 294b647684 fix SHV Dillon Beliveau 2020-08-17 10:57:55 -04:00
  • b7f3b7a494 fix LHV Dillon Beliveau 2020-08-17 10:47:04 -04:00
  • dc6945e629 basic, probably broken, LHV/SHV Dillon Beliveau 2020-08-16 10:54:17 -04:00
  • 20364472bd Remove all #include ".. - statements Dillon Beliveau 2020-08-16 10:34:12 -04:00
  • d482e327ab add common to include path Dillon Beliveau 2020-08-16 10:18:32 -04:00
  • 0ba8f0811e VRCP, VRSQ Dillon Beliveau 2020-08-12 19:30:06 -04:00
  • 983071e913 fix VRSQH, VRSQL, VRCPL Dillon Beliveau 2020-08-12 19:27:53 -04:00
  • 30f0e75f18 cleanup, change exit(0) lines back to logfatal lines Dillon Beliveau 2020-08-06 18:12:55 -04:00
  • 15e24b3932 VMRG clears VCO Dillon Beliveau 2020-08-05 20:40:45 -04:00
  • f01d688f4a cleanup comment Dillon Beliveau 2020-08-04 21:36:08 -04:00
  • 4c84e86682 VRSQ Dillon Beliveau 2020-08-04 21:35:54 -04:00
  • dbe173e77b use correct table Dillon Beliveau 2020-08-04 21:33:15 -04:00
  • 87c81b7d72 don't sign extend here Dillon Beliveau 2020-08-04 20:27:47 -04:00
  • 3951613b99 fix VGE Dillon Beliveau 2020-08-04 20:21:37 -04:00
  • 333e103c37 fix VCL Dillon Beliveau 2020-08-04 20:14:24 -04:00
  • 9e145d8ea1 RSP CTC2 Dillon Beliveau 2020-08-04 20:03:29 -04:00
  • 94ddba1214 sign extend in CFC2 Dillon Beliveau 2020-08-04 18:45:05 -04:00
  • 14ebfe9916 fix sbv Dillon Beliveau 2020-08-04 17:41:26 -04:00
  • dc5be368bc lbv Dillon Beliveau 2020-08-04 17:40:51 -04:00
  • bbf8b75a52 forgot this bit of RSP SLT Dillon Beliveau 2020-08-03 19:49:16 -04:00
  • 32a4d9d9a4 writing to DPC STATUS Dillon Beliveau 2020-08-03 19:48:27 -04:00
  • 356bf82685 RSP SLT Dillon Beliveau 2020-08-03 19:48:13 -04:00
  • 12cf81d082 Fix LRV Dillon Beliveau 2020-08-03 19:34:53 -04:00
  • 41b63fab99 update screen when VSync hit. Check VI interrupts and VSync at all appropriate times. Update screen when RDP plugin says to Dillon Beliveau 2020-08-03 19:08:47 -04:00
  • ba1ed36af9 don't run angrylion with parallel mode on Dillon Beliveau 2020-08-03 19:06:51 -04:00
  • c3dbccd165 kinda broken LRV/SRV Dillon Beliveau 2020-08-02 18:07:09 -04:00
  • 76a827d2a7 fix LSV Dillon Beliveau 2020-08-02 15:50:13 -04:00
  • 49010e4586 fix SLV Dillon Beliveau 2020-08-02 15:07:28 -04:00
  • a43bf7410b fix LLV Dillon Beliveau 2020-08-02 15:06:11 -04:00
  • 9cc98cd798 fix LPV Dillon Beliveau 2020-08-02 14:57:29 -04:00
  • be121b7148 fix MFC2 Dillon Beliveau 2020-08-02 14:50:58 -04:00
  • 3d809abea0 fix MTC2 Dillon Beliveau 2020-08-02 14:46:50 -04:00
  • f164fc0ba3 more progress on STV, still not fully working Dillon Beliveau 2020-08-02 14:42:10 -04:00
  • 8f9966057e label columns Dillon Beliveau 2020-08-02 14:19:36 -04:00
  • 498820e49c don't run any other RSP tests if one fails - doesn't make any sense, since they depend on the output of the previous test. Dillon Beliveau 2020-08-02 14:07:34 -04:00
  • a3648fecf6 Working on STV. Only consider top two bits of VT, do wrapping at byte level Dillon Beliveau 2020-08-02 13:19:44 -04:00
  • 660b7ee2f6 remove this code that was accidentally left in Dillon Beliveau 2020-08-02 09:36:01 -04:00
  • 0ad862cb74 quiet down plugin interface logging Dillon Beliveau 2020-08-02 09:35:50 -04:00
  • 02354069c8 sign extend multiply accumulator Dillon Beliveau 2020-08-02 09:35:38 -04:00