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  • 999562468c mask Count reg Dillon Beliveau 2020-12-27 02:14:49 -05:00
  • 24e9d8f6cc hack: write RDRAM size to 0x318 after first PI DMA Dillon Beliveau 2020-12-27 02:14:28 -05:00
  • 9ef2d59872 RI regs are writable, and are initialized to certain values Dillon Beliveau 2020-12-27 02:08:33 -05:00
  • 3cb763a164 TEQ in JIT Dillon Beliveau 2020-12-27 01:36:36 -05:00
  • 4b9224067c TEQ in interpreter Dillon Beliveau 2020-12-27 01:18:16 -05:00
  • 6a10e1c50a XKUSEG probe TLB Dillon Beliveau 2020-12-26 23:18:20 -05:00
  • d69ab0cd32 64 bit addressing working Dillon Beliveau 2020-12-26 23:15:03 -05:00
  • 6e8bfa93fd frameworking out 64 bit addressing Dillon Beliveau 2020-12-26 22:19:21 -05:00
  • b5c2b84261 NaN checks in FPU instructions Dillon Beliveau 2020-12-26 19:36:17 -05:00
  • 51f49b77f5 fix DIV when dividing by zero Dillon Beliveau 2020-12-26 18:48:41 -05:00
  • 5f7399bc7d log rom name Dillon Beliveau 2020-12-26 18:35:42 -05:00
  • 34fc64a2d5 CP0 fixes Dillon Beliveau 2020-12-26 18:33:48 -05:00
  • 4ca695c42f inc PI DRAM and CART addresses by the length Dillon Beliveau 2020-12-26 17:03:52 -05:00
  • 8d932033e9 set wired and context Dillon Beliveau 2020-12-26 17:03:42 -05:00
  • 6bedb31d1e write word to SRAM from 2_1 Dillon Beliveau 2020-12-26 17:01:02 -05:00
  • f6265bbee0 size asserts Dillon Beliveau 2020-12-26 17:00:23 -05:00
  • e228958190 slower, but hopefully more accurate, RSP timing Dillon Beliveau 2020-12-26 15:20:06 -05:00
  • 13ed5844f8 tweaks and cleanup - macros Dillon Beliveau 2020-12-26 15:19:54 -05:00
  • 1331d482d5 support reading more PI DMA regs Dillon Beliveau 2020-12-26 14:02:24 -05:00
  • a59eede65d latest version of parallel-rdp Dillon Beliveau 2020-12-26 14:01:03 -05:00
  • e851332316 cleanup macros Dillon Beliveau 2020-12-26 13:48:19 -05:00
  • a27a0cc9a4 faster srlv, mfhi, mthi, mflo, mtlo Dillon Beliveau 2020-12-26 13:46:28 -05:00
  • 0c00a8b0e4 sllv Dillon Beliveau 2020-12-26 13:38:03 -05:00
  • 9db558df63 faster srav Dillon Beliveau 2020-12-26 13:32:23 -05:00
  • d6160bc298 just warn when byte read from N64DD Dillon Beliveau 2020-12-25 23:52:08 -05:00
  • 82c3791a66 RSP: sltiu, sltu Dillon Beliveau 2020-12-25 22:57:19 -05:00
  • 9bd908793b ldc1/sdc1/lwc1/swc1 exception handling in JIT Dillon Beliveau 2020-12-25 22:43:51 -05:00
  • 8cea5accbd check cp1 exceptions ldc1/sdc1/lwc1/swc1 Dillon Beliveau 2020-12-25 21:55:31 -05:00
  • 7674bd1cac exception fixes/updates Dillon Beliveau 2020-12-25 20:22:25 -05:00
  • e50539acef size assertions Dillon Beliveau 2020-12-25 19:54:02 -05:00
  • b185ffa0f9 check FPU exceptions in CTC1 Dillon Beliveau 2020-12-25 19:13:06 -05:00
  • dfe2b2d8b8 GDB stub updates and fixes Dillon Beliveau 2020-12-25 16:26:38 -05:00
  • 861e04d5e6 allow switching between jit and interpreter without recompiling, debug mode forces interpreter Dillon Beliveau 2020-12-25 14:43:21 -05:00
  • edc809993b don't queue audio if more than half a second is already queued Dillon Beliveau 2020-12-24 18:11:33 -05:00
  • 0f8a3e2ea0 write byte to SRAM in REGION_CART_2_2 Dillon Beliveau 2020-12-24 18:10:54 -05:00
  • 348aad1777 RSP timing tweaks Dillon Beliveau 2020-12-24 18:06:44 -05:00
  • f41cecd264 sram read from cart_2_1 Dillon Beliveau 2020-12-24 18:06:07 -05:00
  • d30a700930 update bus errors/warnings Dillon Beliveau 2020-12-24 16:29:30 -05:00
  • 80c5d7f076 SRAM Dillon Beliveau 2020-12-24 16:25:10 -05:00
  • 89f5cc32fb cleanup a bit of code in dynarec Dillon Beliveau 2020-12-24 00:31:15 -05:00
  • a77cc704c2 USR2 turns logging back off Dillon Beliveau 2020-12-24 00:31:02 -05:00
  • 087509f096 remove 2 log lines Dillon Beliveau 2020-12-24 00:24:15 -05:00
  • 5583d4fe22 turn on debug logging when USR1 signal received Dillon Beliveau 2020-12-23 22:59:57 -05:00
  • e95ce62921 JIT: make branches to self take 64 cycles in the, macro some switch statements Dillon Beliveau 2020-12-23 22:41:10 -05:00
  • 2f28a24a2d TLB translations in KSEG3 Dillon Beliveau 2020-12-23 21:30:13 -05:00
  • 3b0ca0a2e1 compile TLBR Dillon Beliveau 2020-12-23 21:30:05 -05:00
  • a16a3bda73 LUI with no UB Dillon Beliveau 2020-12-23 19:50:11 -05:00
  • 608ec61486 only inc count in one place Dillon Beliveau 2020-12-23 19:50:06 -05:00
  • 16a34d43a5 sync up with new jit timings Dillon Beliveau 2020-12-23 19:49:54 -05:00
  • d73b2643c3 return zero when outside of the cart range Dillon Beliveau 2020-12-23 19:15:45 -05:00
  • c9323cd564 ignore some invalid writes Dillon Beliveau 2020-12-23 19:15:31 -05:00
  • 572ff6a998 tlbr seems to work, so enable it Dillon Beliveau 2020-12-23 19:14:36 -05:00
  • 9b5a83201c more portable DMULT and DMULTU Dillon Beliveau 2020-12-23 19:06:21 -05:00
  • d50742f8a2 free objects Dillon Beliveau 2020-12-23 18:21:50 -05:00
  • 91a0fdd697 mask address every time skip is added & correct length register value Dillon Beliveau 2020-12-22 22:15:32 -05:00
  • b9dfa65e81 length reg in SP DMA writes as well Dillon Beliveau 2020-12-22 21:58:31 -05:00
  • 21d244ec02 improve mem force alignment in SP DMAs Dillon Beliveau 2020-12-22 21:56:49 -05:00
  • 51199cc0a0 SP DMA addresses are stored in shadow registers until the DMA runs Dillon Beliveau 2020-12-22 21:46:10 -05:00
  • f28a336f5b these are one register on hardware Dillon Beliveau 2020-12-22 21:02:39 -05:00
  • f5303cb5a8 combine cells Dillon Beliveau 2020-12-22 20:29:44 -05:00
  • 11bba27c24 change theme and formatting of some tables Dillon Beliveau 2020-12-22 19:38:36 -05:00
  • d9cc6edc9d Every MIPS interface register documented Dillon Beliveau 2020-12-22 00:53:16 -05:00
  • 5f72ce7461 more MI docs Dillon Beliveau 2020-12-22 00:42:41 -05:00
  • 458ece5fe9 document one MI register Dillon Beliveau 2020-12-22 00:14:02 -05:00
  • 8e1bd59b04 back to interpreter for these tests Dillon Beliveau 2020-12-21 20:33:50 -05:00
  • 533e4a4294 JIT: dmult, dsra, bltzal Dillon Beliveau 2020-12-21 19:46:59 -05:00
  • 3ea6dde4a7 increment Count correctly in JIT Dillon Beliveau 2020-12-21 19:31:46 -05:00
  • 73560e4a0e BAILZERO macro Dillon Beliveau 2020-12-20 17:20:51 -05:00
  • 36cd6af3f8 remove logs Dillon Beliveau 2020-12-20 17:17:48 -05:00
  • b54e223e1c sra Dillon Beliveau 2020-12-20 17:11:09 -05:00
  • 9d640f5a95 SEAX macro Dillon Beliveau 2020-12-20 16:58:08 -05:00
  • 6bcdc6b081 LOADRAX/SAVERAX macros Dillon Beliveau 2020-12-20 16:54:19 -05:00
  • 0146ae4361 sll/srl Dillon Beliveau 2020-12-20 16:38:18 -05:00
  • e0c3f1ca3c ori/xori Dillon Beliveau 2020-12-20 16:32:13 -05:00
  • e0f89a4775 reorganize Dillon Beliveau 2020-12-20 16:23:31 -05:00
  • 74f5a832ab faster compiler for andi Dillon Beliveau 2020-12-20 16:16:56 -05:00
  • 1122d6732c fix warning Dillon Beliveau 2020-12-20 16:16:48 -05:00
  • 5ab318ae72 macroin' and fixin' - (d)addi(u) shouldn't write to r0 Dillon Beliveau 2020-12-20 16:06:35 -05:00
  • b75d08ac59 fix addi/addiu Dillon Beliveau 2020-12-20 15:52:23 -05:00
  • a675c11fd0 test_rom uses dynarec Dillon Beliveau 2020-12-20 15:52:10 -05:00
  • f0c19ba275 addi/addiu don't use handlers at all Dillon Beliveau 2020-12-20 14:43:09 -05:00
  • df4364c000 always bounds-check ROM Dillon Beliveau 2020-12-17 23:43:41 -05:00
  • 8eae9a3dda Function for releasing RSP semaphore Dillon Beliveau 2020-12-17 23:42:58 -05:00
  • 040bb6f0c6 Revert "don't queue samples if we already have a full second of audio available" Dillon Beliveau 2020-12-13 17:45:16 -05:00
  • 0d9d680cbb latest version of parallel-rdp Dillon Beliveau 2020-12-13 15:03:48 -05:00
  • 8df492a53a load pif rom if it exists Dillon Beliveau 2020-12-13 15:03:41 -05:00
  • 2f15a49a68 fix build on Linux Dillon Beliveau 2020-12-13 14:56:16 -05:00
  • ea5df1d417 Merge branch 'master' into windows-port Dillon Beliveau 2020-12-13 14:36:08 -05:00
  • fdd544e75b commented out definitions Dillon Beliveau 2020-12-13 14:35:50 -05:00
  • 55454cbad4 use MAIN_DEPENDENCY Dillon Beliveau 2020-12-13 14:35:41 -05:00
  • 3861a8e884 CMake updates to work with Ninja generator Dillon Beliveau 2020-12-13 14:03:01 -05:00
  • 20e3bb388b better name Dillon Beliveau 2020-12-13 13:50:35 -05:00
  • eb6c41a592 don't queue samples if we already have a full second of audio available Dillon Beliveau 2020-12-13 13:49:51 -05:00
  • a20ad247ba all macro compiles together Dillon Beliveau 2020-12-13 13:23:10 -05:00
  • 78ac1f50c8 better variable name to not confuse myself Dillon Beliveau 2020-12-13 02:01:45 -05:00
  • cc87506698 reset cpu steps to zero to not run too many RSP steps when it's enabled after being disabled for a while Dillon Beliveau 2020-12-13 01:40:08 -05:00
  • 7509cb5410 timing tweaks in logtester Dillon Beliveau 2020-12-13 01:38:16 -05:00
  • 7f9abd4e9d when CP1 disabled, don't execute the instruction at all Dillon Beliveau 2020-12-13 01:36:53 -05:00
  • 0c64e52422 eax and notes Dillon Beliveau 2020-12-13 01:36:08 -05:00
  • a56a9594e5 use correct name Dillon Beliveau 2020-12-13 01:35:58 -05:00