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Author SHA1 Message Date
Dillon Beliveau
54a65197dd set entry hi correctly 2021-04-10 16:59:41 -04:00
Dillon Beliveau
8d93188339 bump upper bound 2021-04-10 16:24:02 -04:00
Dillon Beliveau
d0618585f0 tlbwr + tlb exceptions on lwc1 2021-04-10 15:45:54 -04:00
Dillon Beliveau
cb47db1c34 TLB exceptions kinda working 2021-04-10 15:05:28 -04:00
Dillon Beliveau
382f9ededc Ogre battle 64 to game db 2021-04-10 12:01:16 -04:00
Dillon Beliveau
21664896ec dump TLB state on errors 2021-04-10 12:01:00 -04:00
Dillon Beliveau
a58359160d F-Zero X to issues log 2021-04-10 10:10:12 -04:00
Dillon Beliveau
389904a311 0x05xxxxxx is the 64DD 2021-04-10 10:03:11 -04:00
Dillon Beliveau
734586bdea need to go through DMA to access SRAM 2021-04-10 01:41:28 -04:00
Dillon Beliveau
a46a734d14 DSRAV 2021-04-10 01:17:52 -04:00
Dillon Beliveau
c0e1607df9 initialize SRAM to all 0xFFs 2021-04-10 00:51:37 -04:00
Dillon Beliveau
c7d8dceab8 support dumping RDRAM 2021-04-09 21:32:45 -04:00
Dillon Beliveau
318430a3e4 latest version of parallel-rdp 2021-04-06 19:32:13 -04:00
Dillon Beliveau
68d3dc7b27 bump parallel-rdp a few commits 2021-04-04 15:58:23 -04:00
Dillon Beliveau
42410be8cd Resident Evil 2 to game DB 2021-04-04 14:51:44 -04:00
Dillon Beliveau
4e4c1347cd Basic idle loop detection 2021-04-04 08:50:09 -04:00
Dillon Beliveau
b282d1fa1c interpreter matches jit timing (supports pal, etc) 2021-04-04 07:27:02 -04:00
Dillon Beliveau
06b9bf0a37 Fix CP1 round instructions 2021-04-03 13:21:06 -04:00
Dillon Beliveau
083d8f7287 Log how many bytes we missed 2021-04-03 12:18:11 -04:00
Dillon Beliveau
84506e44d6 audio adjustments 2021-04-03 12:16:12 -04:00
Dillon Beliveau
1203508cea correct stack alignment in jit 2021-04-02 17:00:11 -04:00
Dillon Beliveau
f2cb612de8 JIT exception fixes 2021-03-30 22:46:16 -04:00
Dillon Beliveau
f3aaa41c6e don't trigger compare interrupts twice in interpreter 2021-03-28 17:01:04 -04:00
Dillon Beliveau
28d2e4bd08 cp0 wait in interpreter 2021-03-28 17:00:43 -04:00
Dillon Beliveau
c083fc0d19 cast to dword 2021-03-28 16:39:49 -04:00
Dillon Beliveau
5f674f8292 count is shifted left by 1 2021-03-28 15:45:43 -04:00
Dillon Beliveau
399919e0f7 TLB exception in LW 2021-03-28 15:41:34 -04:00
Dillon Beliveau
2efaca1ccb cp0 wait instruction in jit 2021-03-28 14:46:42 -04:00
Dillon Beliveau
98732192ef bus changes to help test rom get past everdrive detection 2021-03-28 14:24:49 -04:00
Dillon Beliveau
6a40bcbbf2 syscall instr in jit 2021-03-28 14:24:33 -04:00
Dillon Beliveau
a33bf11ad9 rectangles choose fill color based on addr as well 2021-03-28 14:14:36 -04:00
Dillon Beliveau
1fc38bbcf4 correct and speedup triangle fill 2021-03-28 14:07:37 -04:00
Dillon Beliveau
9235b2467b Fill rectangle corrections 2021-03-28 13:48:33 -04:00
Dillon Beliveau
c15356d4e9 fix typo 2021-03-27 21:23:28 -04:00
Dillon Beliveau
d333afca50 extract z buffer coefficients 2021-03-27 15:22:41 -04:00
Dillon Beliveau
976ff1f637 reusable triangle edgewalker 2021-03-27 13:47:44 -04:00
Dillon Beliveau
619e465805 reusable get_edge_coefficients 2021-03-27 12:45:28 -04:00
Dillon Beliveau
e565e6412e fine-tune audio, fix an issue 2021-03-27 12:13:24 -04:00
Dillon Beliveau
1168afc640 Don't set C and CXX standards 2021-03-27 10:15:43 -04:00
Dillon Beliveau
78c0f66c90 fpu unordered compares in jit 2021-03-21 15:36:33 -04:00
Dillon Beliveau
991ad5ee33 rudimentary ISViewer support 2021-03-21 15:32:57 -04:00
Dillon Beliveau
91647d7ed1 FPU unordered compare 2021-03-21 14:56:31 -04:00
Dillon Beliveau
9b2309f408 multiply-accumulate SISD version fixes 2021-03-21 14:07:29 -04:00
Dillon Beliveau
a76bfd20a9 vmadm overflow test updates, comment out failure case for now 2021-03-20 20:45:46 -04:00
Dillon Beliveau
734686e984 remove junk assert 2021-03-20 18:51:46 -04:00
Dillon Beliveau
2187d40f5e remove commented line 2021-03-20 17:47:34 -04:00
Dillon Beliveau
2c4df128b1 RSP full logging 2021-03-20 17:47:29 -04:00
Dillon Beliveau
894c210ec3 still want to fail when not the expected case 2021-03-20 17:43:58 -04:00
Dillon Beliveau
71630f6171 don't fail the test when the SIMD implementation is used (for now) 2021-03-20 17:43:19 -04:00
Dillon Beliveau
ec11e80f23 olt_d and ult_d 2021-03-20 17:39:31 -04:00