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Author SHA1 Message Date
Dillon Beliveau
395c842c58 swapping between roms deals with different backup files correctly 2021-01-19 22:12:08 -05:00
Dillon Beliveau
f687ac01b6 file browser, and allow swapping out ROM 2021-01-19 21:53:45 -05:00
Dillon Beliveau
58cb143f83 Display UI on a blank screen when no ROM loaded 2021-01-19 21:09:22 -05:00
Dillon Beliveau
6c51fca0b4 imgui metrics with ImPlot 2021-01-19 00:06:31 -05:00
Dillon Beliveau
b138a4de8b start working on UI 2021-01-18 21:34:21 -05:00
Dillon Beliveau
9d002efc9f finally got imgui working 2021-01-18 21:10:54 -05:00
Dillon Beliveau
1c9bb1a54c missed some zeroes 2021-01-18 14:08:44 -05:00
Dillon Beliveau
dd8eb8d918 use memcpy for HLEing the pif rom's DMA 2021-01-17 17:08:24 -05:00
Dillon Beliveau
bf03a6219e buggy round instructions 2021-01-17 16:47:24 -05:00
Dillon Beliveau
1901617402 these were wrong, so mark them as unimplemented again 2021-01-17 16:25:51 -05:00
Dillon Beliveau
fde580b70c stub cp1 round instructions 2021-01-17 16:21:40 -05:00
Dillon Beliveau
78077e7e55 exception updates & implement TRAP exception 2021-01-17 15:35:35 -05:00
Dillon Beliveau
0d28224371 do work in rax 2021-01-17 15:06:25 -05:00
Dillon Beliveau
6bdaef1bc6 these don't sign extend 2021-01-17 14:21:13 -05:00
Dillon Beliveau
ed3b92c014 dsrl32, dsra32 2021-01-17 14:03:01 -05:00
Dillon Beliveau
e4747d501d fix doubleword shifts, add dsll32 2021-01-17 14:01:46 -05:00
Dillon Beliveau
351b26f04f more fast versions of instructions 2021-01-17 13:48:51 -05:00
Dillon Beliveau
5a0b1f551b Merge branch 'register-allocation' 2021-01-17 12:44:01 -05:00
Dillon Beliveau
dfebb66bc1 variable shifts, use al in slti(u) 2021-01-17 12:34:25 -05:00
Dillon Beliveau
310d3669fb upgrade dynasm, don't use rcx for register allocation 2021-01-17 12:25:04 -05:00
Dillon Beliveau
0da16e7289 check and flush even when just loading one register 2021-01-17 01:38:10 -05:00
Dillon Beliveau
84b2dd0b7d mfhi/mthi/mflo/mtlo, framework for r_type 2021-01-17 01:34:58 -05:00
Dillon Beliveau
42a62a8c5f fast slti, sltiu, sll, srl, sra 2021-01-17 00:57:36 -05:00
Dillon Beliveau
a86b429426 more reorganizing and cleanup 2021-01-16 23:43:27 -05:00
Dillon Beliveau
42a1a9214d just do the movsxd 2021-01-16 23:40:41 -05:00
Dillon Beliveau
8ecc09f72a reorganize and cleanup 2021-01-16 23:22:20 -05:00
Dillon Beliveau
06114a767b flush all regs after branch likely 2021-01-16 23:16:57 -05:00
Dillon Beliveau
a87cb0cfbc andi + ori working 2021-01-16 23:15:57 -05:00
Dillon Beliveau
0fa9a98bbc register allocation seems to be working, using only low registers for now 2021-01-16 23:10:14 -05:00
Dillon Beliveau
2a4cebae80 fast ori 2021-01-16 20:59:25 -05:00
Dillon Beliveau
5663add43f working with only fast andi 2021-01-16 20:57:16 -05:00
Dillon Beliveau
41f4c211d0 halfway to register allocation 2021-01-16 19:19:32 -05:00
Dillon Beliveau
bf0cd262c9 frameworking for register allocation 2021-01-16 15:51:19 -05:00
Dillon Beliveau
1df95a9a7f Corrections and clarity for boot process doc 2021-01-16 11:09:22 -05:00
Dillon Beliveau
e0b7b339e0 make dasm_State a static variable 2021-01-16 02:27:35 -05:00
Dillon Beliveau
fa6b352231 use %lX instead of X where appropriate 2021-01-16 02:05:08 -05:00
Dillon Beliveau
12f4c0d546 quiet down a GCC bitfield warning 2021-01-16 02:04:03 -05:00
Dillon Beliveau
68c6991eb2 kirby to game db 2021-01-16 01:47:22 -05:00
Dillon Beliveau
e354bfbb6c don't emit tons of PC advancing code. only works on clang so far 2021-01-16 00:42:39 -05:00
Dillon Beliveau
b961e1dc7f flush PC before branches 2021-01-15 20:49:56 -05:00
Dillon Beliveau
62fc0554a5 flush prev pc before exceptions 2021-01-15 20:48:05 -05:00
Dillon Beliveau
3085fc8d41 PC is 64 bit now 2021-01-15 20:47:16 -05:00
Dillon Beliveau
577d210059 faster slti/sltiu 2021-01-15 20:00:36 -05:00
Dillon Beliveau
eded67b2f5 remove unnecessary emitted code 2021-01-14 17:34:23 -05:00
Dillon Beliveau
c2340c86aa minor cleanups 2021-01-12 23:01:41 -05:00
Dillon Beliveau
0d14f74c23 simple IR 2021-01-12 22:30:17 -05:00
Dillon Beliveau
380ba7f7c0 rest of compile logic extracted to dynarec.c 2021-01-11 22:05:37 -05:00
Dillon Beliveau
e2b7a434ae begin separating emitter from main dynarec logic 2021-01-11 21:21:05 -05:00
Dillon Beliveau
1030723684 don't die when reading from these regions 2021-01-09 14:37:54 -05:00
Dillon Beliveau
8227ed98c3 more games to game db 2021-01-09 14:20:31 -05:00