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Author SHA1 Message Date
Dillon Beliveau
a2873231a5 Add windows debug CI 2023-07-06 23:49:28 -04:00
Dillon Beliveau
6502f7d2f1 Fix two implicit fallthrough errors 2023-05-18 23:16:20 -07:00
Dillon Beliveau
44024f14f7
Merge pull request #42 from OFFTKP/master 
Eliminate evil implicit fallthrough
 2023-05-19 02:15:49 -04:00
offtkp
725c10e1fb Eliminate evil implicit fallthrough 2023-05-19 00:45:12 +03:00
Dillon Beliveau
d7576b4379
Merge pull request #41 from OFFTKP/master 
Support reading of ADDR_VI_H_START_REG
 2023-05-03 17:03:44 -04:00
offtkp
db288ef0cb Support reading of ADDR_VI_H_START_REG 
The libdragon example test roms read from this register during
initialization
 2023-05-03 17:38:53 +03:00
Dillon Beliveau
41708b9350 recording demos 2023-04-29 11:16:16 -07:00
Dillon Beliveau
e267984840
Merge pull request #39 from Dillonb/accurate_fpu 
Accurate fpu
 2023-03-18 15:57:28 -07:00
Dillon Beliveau
bbd87af7d4 Fix FPU on Windows 2023-03-18 15:52:01 -07:00
Dillon Beliveau
0fd0988189 Fix CVT overflow checks 2023-03-18 11:29:31 -07:00
Dillon Beliveau
b701312282 set_cause_cvt_l_d takes a double 2023-03-18 10:25:42 -07:00
Dillon Beliveau
52bf0d8048 trunc.l, round.l, ceil.l, floor.l, cvt.l wip 2023-03-13 00:05:52 -07:00
Dillon Beliveau
71ccc8d94a trunc.w, round.w, ceil.w, floor.w, cvt.w complete 2023-03-12 22:24:28 -07:00
Dillon Beliveau
8b14b3d369 updates to trunc.w, round.w, ceil.w, floor.w, cvt.w. Not quite done yet 2023-03-12 21:52:49 -07:00
Dillon Beliveau
0bcf8902a8 cvt_w_s, cvt_w_d, remove last remaining NaN asserts 2023-03-12 21:42:11 -07:00
Dillon Beliveau
2e633dac5b cvt.s.fmt, cvt.d.fmt 2023-03-12 21:12:31 -07:00
Dillon Beliveau
0a8a014443 MFC1/DMFC1/MTC1/DMTC1 preserve cause 2023-03-12 20:53:16 -07:00
Dillon Beliveau
8574cc5f70 actually, this is the behavior of all invalid FPU operations 2023-03-12 20:53:00 -07:00
Dillon Beliveau
74d546c132 DCFC1/DCTC1 throw unimplemented exception 2023-03-12 20:21:32 -07:00
Dillon Beliveau
be698f6486 all compare instructions 2023-03-12 20:21:05 -07:00
Dillon Beliveau
2e6ca46a9b exceptions and failure cases for mul/div/sqrt/abs/neg + fpu mov preserves cause 2023-03-12 18:07:46 -07:00
Dillon Beliveau
8bd11e1c05 handle FE_UNDERFLOW better 2023-03-12 18:06:37 -07:00
Dillon Beliveau
ca9bf27f56 macro for FPU ops, use for add.s/d, sub.s/d 2023-03-12 17:13:19 -07:00
Dillon Beliveau
1152761f91 exceptions and failure cases for add.d 2023-03-12 16:33:20 -07:00
Dillon Beliveau
583ea15257 exceptions and failure cases for add.s 2023-03-12 16:13:28 -07:00
Dillon Beliveau
bf820b2d96 fix FPU exceptions - unimplemented operation should always be enabled 2023-03-12 14:05:43 -07:00
Dillon Beliveau
5837f37998 implement ceil.l.d, ceil.w.d, floor.l.d, floor.w.d 2023-03-12 14:05:30 -07:00
Dillon Beliveau
9347c9cb61 fix 64 bit floating point register accesses 2023-03-12 13:55:45 -07:00
Dillon Beliveau
059fbf2bfa fix 32 bit floating point register accesses 2023-03-12 13:25:51 -07:00
Dillon Beliveau
fe2a97a80d FPU accuracy updates 2023-03-11 17:53:21 -08:00
Dillon Beliveau
665a1802fe improvements to fpu register access - not quite perfect yet 2023-03-11 16:04:22 -08:00
Dillon Beliveau
1b251a8075 check fpu exception 2023-03-11 16:04:11 -08:00
Dillon Beliveau
48d1cdae70 implement more floor instrs, implement ceil instrs 2023-03-11 14:37:29 -08:00
Dillon Beliveau
9cf8fb0c6e misaligned PC exceptions 2023-03-11 14:11:04 -08:00
Dillon Beliveau
ecbf11149f branch likely should only set bd flag when the branch is taken 2023-03-11 12:41:14 -08:00
Dillon Beliveau
0ca38c593b Upgrade imgui and implot 2023-02-11 12:21:18 -08:00
Dillon Beliveau
2dd8f0b60f dpc start should never change 2022-10-16 10:18:27 -07:00
Dillon Beliveau
bd4ff4a3c2 fix DIV and DDIV 2022-10-16 09:58:34 -07:00
Dillon Beliveau
6cdc45c460 Support capstone dependency on windows 2022-10-09 18:23:09 -07:00
Dillon Beliveau
48b2050492 fix bitfields for Windows 2022-10-04 11:11:11 -07:00
Dillon Beliveau
321fb34383 don't latch PI on ISViewer writes 2022-10-03 23:28:02 -07:00
Dillon Beliveau
0570c4ee1e replace the hack with a slightly less hacky hack 2022-09-18 14:46:06 -07:00
Dillon Beliveau
2517c5912e 16bpp textured rectangles, sorta 2022-09-18 14:29:27 -07:00
Dillon Beliveau
bc7067bac0 load_block, sorta 2022-09-18 14:28:53 -07:00
Dillon Beliveau
c8f676b63b 8bpp/16bpp tile loads 2022-09-18 12:28:19 -07:00
Dillon Beliveau
d9b4e83312 32bpp textured rectangle support in software rdp 2022-09-17 17:54:13 -07:00
Dillon Beliveau
4e2ddfa564 better self-modifying code detection: mark what addresses are code, and only invalidate a dynarec page if one of those is rewritten. 2022-09-11 19:16:04 -07:00
Dillon Beliveau
7e44ce82b7 Stall CPU when reading from PI bus latch 2022-09-10 15:34:21 -07:00
Dillon Beliveau
442ecddf83 Shorten PI bus write time 2022-09-10 15:24:50 -07:00
Dillon Beliveau
2f1217418f Emulate invalid coprocessor instructions 2022-09-10 15:16:33 -07:00