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Author	SHA1	Message	Date
Dillon Beliveau	23f3f3febc	.h files are C	2020-06-17 17:09:16 -04:00
Dillon Beliveau	b559ff39bc	Disassemble as MIPS64	2020-06-16 23:37:58 -04:00
Dillon Beliveau	5a2d7f17b8	this doesn't exist	2020-06-16 23:29:44 -04:00
Dillon Beliveau	d3103526f5	Treat as signed	2020-06-16 23:18:13 -04:00
Dillon Beliveau	89fc2001ed	disassemble if necessary	2020-06-16 20:16:43 -04:00
Dillon Beliveau	e720afb1cb	Got basic graphics working!	2020-06-16 20:03:26 -04:00
Dillon Beliveau	86d229fc08	Stub V_CURRENT and rendering	2020-06-16 17:35:45 -04:00
Dillon Beliveau	e6550af905	J instruction	2020-06-16 17:10:13 -04:00
Dillon Beliveau	8b2fa51e8a	BGTZ, read VI Registers	2020-06-16 00:54:32 -04:00
Dillon Beliveau	8ef3059c61	these should be logtrace	2020-06-16 00:42:56 -04:00
Dillon Beliveau	8d3d689efc	LB	2020-06-16 00:39:50 -04:00
Dillon Beliveau	0f97a7b73d	Stub PIF and VI stuff	2020-06-16 00:32:07 -04:00
Dillon Beliveau	ab2135a1cd	PI status reg writes	2020-06-15 23:20:36 -04:00
Dillon Beliveau	da97800feb	Stub SI regs, ignore word writes to audio interface regs	2020-06-15 23:15:15 -04:00
Dillon Beliveau	a19358789b	Stubbing RSP	2020-06-15 22:54:47 -04:00
Dillon Beliveau	804b898210	Better naming	2020-06-15 21:19:28 -04:00
Dillon Beliveau	a5cea9b366	Prefix opcode functions with mips32_	2020-06-15 21:14:27 -04:00
Dillon Beliveau	d4690e0ace	BGEZAL	2020-06-15 20:50:32 -04:00
Dillon Beliveau	f4c6907977	More instructions, logging changes	2020-06-15 20:13:57 -04:00
Dillon Beliveau	758ad31b06	Reorganize, add DMAs	2020-06-15 18:25:26 -04:00
Dillon Beliveau	7028e6b81a	Guess it doesn't work on MacOS yet	2020-06-15 17:40:59 -04:00
Dillon Beliveau	b85a0ab89c	Missed a couple GBA -> N64	2020-06-15 17:37:13 -04:00
Dillon Beliveau	13022fd044	Github actions build on Linux/MacOS	2020-06-15 17:36:18 -04:00
Dillon Beliveau	d49e93dde7	Stub PI regs, implement the first one	2020-06-14 17:35:23 -04:00
Dillon Beliveau	852e15f549	Make it through the bootcode now!	2020-06-14 16:00:58 -04:00
Dillon Beliveau	1936990ef1	Stub cache opcode	2020-06-14 14:32:55 -04:00
Dillon Beliveau	b11fdf25d0	Comment this out for now	2020-06-14 13:50:02 -04:00
Dillon Beliveau	df6167e3c4	Set rd, not rt	2020-06-14 13:49:56 -04:00
Dillon Beliveau	5b02a53cbf	JAL uses branch_abs	2020-06-14 13:41:52 -04:00
Dillon Beliveau	cee0184d71	Register names in debug logs	2020-06-14 13:40:36 -04:00
Dillon Beliveau	6ea88d431f	Debug log lines are green	2020-06-14 12:24:31 -04:00
Dillon Beliveau	e7054a3a48	Fixes for logtester	2020-06-14 12:17:28 -04:00
Dillon Beliveau	0c4fdacc3c	Simple logtester frontend	2020-06-14 11:12:57 -04:00
Dillon Beliveau	6b9c957424	Use a wrapper for get_register as well. Ensure all register accesses are done through wrappers	2020-06-14 10:50:10 -04:00
Dillon Beliveau	63dc86c566	ADD/SLT, read unused	2020-06-13 17:39:59 -04:00
Dillon Beliveau	8df896fb02	First REGIMM instruction: BGEZL	2020-06-13 16:36:06 -04:00
Dillon Beliveau	cef50507f9	Stub REGIMM	2020-06-13 16:32:43 -04:00
Dillon Beliveau	025d693730	lots more instructions	2020-06-13 16:21:00 -04:00
Dillon Beliveau	534707696c	Special instruction decoding	2020-06-13 15:16:51 -04:00
Dillon Beliveau	de01b8fe76	Oops	2020-06-11 23:12:45 -04:00
Dillon Beliveau	ab5389ac3c	SB, RDRAM, bytes	2020-06-11 23:01:42 -04:00
Dillon Beliveau	40894b912f	Finish	2020-06-11 22:39:18 -04:00
Dillon Beliveau	b9cc24e254	Refactoring, branch delay, couple more instructions	2020-06-11 22:36:17 -04:00
Dillon Beliveau	7b85ca3882	SLTI	2020-06-10 22:08:14 -04:00
Dillon Beliveau	227cac9d9f	JAL	2020-06-10 21:56:15 -04:00
Dillon Beliveau	4c769b6c88	More instructions, stub more hardware registers	2020-06-10 21:15:39 -04:00
Dillon Beliveau	8f3d6bfb39	Refactoring, implement a few more instructions	2020-06-10 16:17:04 -04:00
Dillon Beliveau	77a8ac60ae	BNE, NOP, some debugging notes	2020-06-10 02:58:53 -04:00
Dillon Beliveau	8b002571e8	Stub some RDRAM interface registers	2020-06-10 02:30:07 -04:00
Dillon Beliveau	f43d09bf69	Decode and execute a few instructions	2020-06-10 00:54:09 -04:00