Emulation/n64
1
0
Fork 0
mirror of https://github.com/Dillonb/n64.git synced 2025-04-02 10:42:08 -04:00
Code Issues Projects Releases Packages Wiki Activity
1157 commits 16 branches 0 tags 17 MiB
Commit graph

1157 commits

This branch
This branch
All branches
Author SHA1 Message Date
Dillon Beliveau
edfd4dc335 Include stripped-down versions of the CPU tests 2020-06-30 20:05:35 -04:00
Dillon Beliveau
f6154f1cc5 CPU tests are file based 2020-06-29 23:16:04 -04:00
Dillon Beliveau
5137e8772a More tests 2020-06-28 12:25:13 -04:00
Dillon Beliveau
f759441c00 Start stubbing tests 2020-06-28 12:04:03 -04:00
Dillon Beliveau
1a4a8b9ce3 DSLLV 2020-06-27 22:54:03 -04:00
Dillon Beliveau
42a62c8085 Controller/PIF tweaking/flailing 2020-06-27 22:13:11 -04:00
Dillon Beliveau
0ae1f77b50 more buttons, pif improvements. controllers still broken 2020-06-27 18:59:24 -04:00
Dillon Beliveau
103e85bc68 c_sub 2020-06-27 13:34:01 -04:00
Dillon Beliveau
06e8cd0d3f c_lt 2020-06-27 13:28:26 -04:00
Dillon Beliveau
75a0a7fbb0 Fix controllers 2020-06-27 13:26:03 -04:00
Dillon Beliveau
01faefa1d4 Remove mock controller data 2020-06-27 11:19:23 -04:00
Dillon Beliveau
055c2829d1 Fix 16 bit graphics. Begin implementing controllers 2020-06-27 01:22:34 -04:00
Dillon Beliveau
ff4df4fb22 Fix DMA 2020-06-25 00:45:05 -04:00
Dillon Beliveau
c2516ed8cf Mock controller 2020-06-25 00:44:09 -04:00
Dillon Beliveau
ddd09844d0 Fix bugs, add instructions, add restrictions to CP0 writes 2020-06-25 00:42:40 -04:00
Dillon Beliveau
b1f1810003 Fix sign extension bug 2020-06-24 21:31:38 -04:00
Dillon Beliveau
920cb73080 Fix SH 2020-06-24 00:45:20 -04:00
Dillon Beliveau
1fad26a879 Mock audio, lotsa tweaks 2020-06-24 00:20:57 -04:00
Dillon Beliveau
3ab4224fb6 Quieter logs 2020-06-24 00:15:29 -04:00
Dillon Beliveau
6fc41e98ed Interrupt logging, DP interrupt 2020-06-23 22:22:39 -04:00
Dillon Beliveau
e8db7847cb Automatically adjust texture width 2020-06-23 22:22:29 -04:00
Dillon Beliveau
6147a9b0d9 use wrapper method 2020-06-23 22:20:23 -04:00
Dillon Beliveau
8d24c34f1b less messy 2020-06-23 22:20:12 -04:00
Dillon Beliveau
106800e23e Fix LWL/LWR/SWL/SWR 2020-06-23 22:19:50 -04:00
Dillon Beliveau
5800fa4b73 BLTZ, BLTZL, MOV.S, MOV.D, JALR 2020-06-22 21:00:36 -04:00
Dillon Beliveau
50882d8f8d LWU, fix interrupts, mock AI status reg 2020-06-22 20:44:07 -04:00
Dillon Beliveau
4b4e8e8f5c Fix sign extension 2020-06-22 18:59:27 -04:00
Dillon Beliveau
f4377266fb each instruction takes two cycles 2020-06-22 18:41:01 -04:00
Dillon Beliveau
115f7646c3 interrupt tweaks 2020-06-22 18:34:34 -04:00
Dillon Beliveau
96960cf16e Make RDRAM 8MB 2020-06-21 22:43:51 -04:00
Dillon Beliveau
882f1cfcb7 Fix TRUNC, fix printf tokens 2020-06-21 15:01:13 -04:00
Dillon Beliveau
b42f4aca15 <Good commit message> 2020-06-21 05:33:39 -04:00
Dillon Beliveau
c53b3d6f12 Stub out args for float instructions too 2020-06-21 03:01:20 -04:00
Dillon Beliveau
a467eb0ded more FPU stubbin, C_LE, BC1T, BC1F 2020-06-21 03:00:08 -04:00
Dillon Beliveau
dd61f34401 Oops 2020-06-21 02:42:41 -04:00
Dillon Beliveau
308695f4c5 Instruction decoding fixes, FPU stuff 2020-06-21 02:42:03 -04:00
Dillon Beliveau
89d2a7a642 interrupts, exceptions, more instructions, logtester initializes registers to ares' values, etc etc 2020-06-21 00:07:59 -04:00
Dillon Beliveau
e2e3b0fd3f First floating point opcodes: mul.s and mul.d 2020-06-20 00:29:57 -04:00
Dillon Beliveau
a4b92a03c2 More instructions, probably broken exception handling, floating point stuff 2020-06-18 22:18:58 -04:00
Dillon Beliveau
ddc0dc2cdb SH, SRA, 16 bit reads/writes 2020-06-18 20:25:43 -04:00
Dillon Beliveau
9b7c8406db New instructions, bug fixes, allowing access to more registers 2020-06-18 20:02:15 -04:00
Dillon Beliveau
6c0131390c CFC1, CTC1 2020-06-18 00:49:12 -04:00
Dillon Beliveau
0c941f8754 Redo how CP0 registers are stored, implement status register 2020-06-17 23:46:42 -04:00
Dillon Beliveau
8c16c4fe05 Fix coprocessor instruction decoding. MFC0 instruction implemented 2020-06-17 23:23:57 -04:00
Dillon Beliveau
ea896e7975 Doubleword adds 2020-06-17 23:00:00 -04:00
Dillon Beliveau
1d5b6d4da3 Show disassembly in level-2 decode functions too 2020-06-17 22:38:11 -04:00
Dillon Beliveau
5e76ba9e91 Load and store doublewords 2020-06-17 22:27:58 -04:00
Dillon Beliveau
814ec3550a Rename all MIPS32 stuff to just MIPS 2020-06-17 22:05:00 -04:00
Dillon Beliveau
bff8fa082c Fixing sign extension errors 2020-06-17 21:53:40 -04:00
Dillon Beliveau
c73ab53832 CP0 work, all instrs run with 64 bit registers 2020-06-17 21:30:44 -04:00