Commit graph

1157 commits

Author SHA1 Message Date
Dillon Beliveau
ec26947761 toggle framerate unlocking with u 2021-04-18 15:26:40 -04:00
Dillon Beliveau
5c14b361d4 div fix INT_MIN/-1, ddiv fix divide by zero 2021-04-18 14:34:11 -04:00
Dillon Beliveau
f0ace0c79a fix div/divu 2021-04-18 14:06:58 -04:00
Dillon Beliveau
69102d37f0 divu/ddivu fixes 2021-04-18 13:47:15 -04:00
Dillon Beliveau
e54955317a only persist mempack data if any data changed 2021-04-17 09:46:40 -04:00
Dillon Beliveau
d6a54a9323 j/jal actually work in 64 bit mode 2021-04-17 09:21:55 -04:00
Dillon Beliveau
8a007f104e j/jal work in 64 bit mode 2021-04-17 09:08:54 -04:00
Dillon Beliveau
02431a272d WWF: No Mercy to game db 2021-04-17 09:04:15 -04:00
Dillon Beliveau
c7ae82acaf use COPx naming convention in docs 2021-04-17 09:04:06 -04:00
Dillon Beliveau
72f77a2a04
Update boot_process.rst 2021-04-12 10:12:11 -04:00
Dillon Beliveau
8e9c4a88e1 DSRAV uses the low 6 bits 2021-04-11 21:04:53 -04:00
Dillon Beliveau
a907738f36 rdram dump code to n64mem.c 2021-04-11 16:09:23 -04:00
Dillon Beliveau
bf300e2e1f Exception documentation 2021-04-11 14:33:42 -04:00
Dillon Beliveau
abbfb046a2 fix wording a little 2021-04-11 13:20:34 -04:00
Dillon Beliveau
fd47bed4c4 more clearly mark when we switch to talking about the CPU internals 2021-04-11 13:17:12 -04:00
Dillon Beliveau
6051b8fecb interrupts 2021-04-11 13:13:52 -04:00
Dillon Beliveau
8a83990069 Document more CPU stuff 2021-04-11 12:10:30 -04:00
Dillon Beliveau
7057005539 update memory map with locations of N64DD stuff 2021-04-11 11:49:02 -04:00
Dillon Beliveau
42e3a998c2 TODOs for rest of VI registers 2021-04-11 11:32:53 -04:00
Dillon Beliveau
0b0444845b document VI_STATUS_REG 2021-04-11 11:06:59 -04:00
Dillon Beliveau
54a65197dd set entry hi correctly 2021-04-10 16:59:41 -04:00
Dillon Beliveau
8d93188339 bump upper bound 2021-04-10 16:24:02 -04:00
Dillon Beliveau
d0618585f0 tlbwr + tlb exceptions on lwc1 2021-04-10 15:45:54 -04:00
Dillon Beliveau
cb47db1c34 TLB exceptions kinda working 2021-04-10 15:05:28 -04:00
Dillon Beliveau
382f9ededc Ogre battle 64 to game db 2021-04-10 12:01:16 -04:00
Dillon Beliveau
21664896ec dump TLB state on errors 2021-04-10 12:01:00 -04:00
Dillon Beliveau
a58359160d F-Zero X to issues log 2021-04-10 10:10:12 -04:00
Dillon Beliveau
389904a311 0x05xxxxxx is the 64DD 2021-04-10 10:03:11 -04:00
Dillon Beliveau
734586bdea need to go through DMA to access SRAM 2021-04-10 01:41:28 -04:00
Dillon Beliveau
a46a734d14 DSRAV 2021-04-10 01:17:52 -04:00
Dillon Beliveau
c0e1607df9 initialize SRAM to all 0xFFs 2021-04-10 00:51:37 -04:00
Dillon Beliveau
c7d8dceab8 support dumping RDRAM 2021-04-09 21:32:45 -04:00
Dillon Beliveau
318430a3e4 latest version of parallel-rdp 2021-04-06 19:32:13 -04:00
Dillon Beliveau
68d3dc7b27 bump parallel-rdp a few commits 2021-04-04 15:58:23 -04:00
Dillon Beliveau
42410be8cd Resident Evil 2 to game DB 2021-04-04 14:51:44 -04:00
Dillon Beliveau
4e4c1347cd Basic idle loop detection 2021-04-04 08:50:09 -04:00
Dillon Beliveau
b282d1fa1c interpreter matches jit timing (supports pal, etc) 2021-04-04 07:27:02 -04:00
Dillon Beliveau
06b9bf0a37 Fix CP1 round instructions 2021-04-03 13:21:06 -04:00
Dillon Beliveau
083d8f7287 Log how many bytes we missed 2021-04-03 12:18:11 -04:00
Dillon Beliveau
84506e44d6 audio adjustments 2021-04-03 12:16:12 -04:00
Dillon Beliveau
1203508cea correct stack alignment in jit 2021-04-02 17:00:11 -04:00
Dillon Beliveau
f2cb612de8 JIT exception fixes 2021-03-30 22:46:16 -04:00
Dillon Beliveau
f3aaa41c6e don't trigger compare interrupts twice in interpreter 2021-03-28 17:01:04 -04:00
Dillon Beliveau
28d2e4bd08 cp0 wait in interpreter 2021-03-28 17:00:43 -04:00
Dillon Beliveau
c083fc0d19 cast to dword 2021-03-28 16:39:49 -04:00
Dillon Beliveau
5f674f8292 count is shifted left by 1 2021-03-28 15:45:43 -04:00
Dillon Beliveau
399919e0f7 TLB exception in LW 2021-03-28 15:41:34 -04:00
Dillon Beliveau
2efaca1ccb cp0 wait instruction in jit 2021-03-28 14:46:42 -04:00
Dillon Beliveau
98732192ef bus changes to help test rom get past everdrive detection 2021-03-28 14:24:49 -04:00
Dillon Beliveau
6a40bcbbf2 syscall instr in jit 2021-03-28 14:24:33 -04:00