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Author	SHA1	Message	Date
Dillon Beliveau	bab25d5ffa	rewrite VCH	2020-09-19 20:31:18 -04:00
Dillon Beliveau	d73ecf01de	fix LTE compare in VCL	2020-09-19 20:10:03 -04:00
Dillon Beliveau	5acc66a105	hacky hack, but don't run the RSP for a second step if it's halted	2020-09-19 14:49:56 -04:00
Dillon Beliveau	3c5af03124	fix VCR	2020-09-13 16:31:29 -04:00
Dillon Beliveau	db8ce9e6c3	fix VCL	2020-09-13 13:46:18 -04:00
Dillon Beliveau	7449bebf55	fix VNE	2020-09-13 13:26:51 -04:00
Dillon Beliveau	6159fa9a0f	fix VMOV	2020-09-13 13:07:50 -04:00
Dillon Beliveau	0312bf80c2	set vco.h to zero in VCR	2020-09-13 12:16:49 -04:00
Dillon Beliveau	e4e49cef01	split up vsvtvd macro	2020-09-13 11:54:57 -04:00
Dillon Beliveau	0b889cda77	NOR in a slightly better spot	2020-09-12 19:17:30 -04:00
Dillon Beliveau	c1dfea1716	RSP JALR and NOR	2020-09-12 17:42:33 -04:00
Dillon Beliveau	db58f828d2	add -march=native to compile flags.	2020-09-12 17:30:14 -04:00
Dillon Beliveau	9f043ded4b	fairly broken VCR	2020-09-12 17:29:25 -04:00
Dillon Beliveau	f4351b5146	no e!=0 check in vrsql	2020-09-12 15:11:32 -04:00
Dillon Beliveau	7537f5e098	VADDC lane selection	2020-09-12 15:11:21 -04:00
Dillon Beliveau	1fa7f8dded	VABS	2020-09-12 14:48:01 -04:00
Dillon Beliveau	c6baa1a83e	lane selection in VSUB and VSUBC	2020-09-12 14:42:14 -04:00
Dillon Beliveau	a5a44572ea	lane selection in VAND	2020-09-12 14:11:51 -04:00
Dillon Beliveau	d3aa85ed79	too excited here again	2020-09-12 14:11:09 -04:00
Dillon Beliveau	eaffb22e39	VMOV	2020-09-12 14:10:58 -04:00
Dillon Beliveau	9f2b2eaedb	lane selection vmrg	2020-09-12 14:04:34 -04:00
Dillon Beliveau	625c36b955	lane selection in vmrg	2020-09-12 14:04:03 -04:00
Dillon Beliveau	6365e28f5a	lane selection in vge	2020-09-12 14:01:01 -04:00
Dillon Beliveau	b0baf406f8	got a little too excited with these	2020-09-12 13:59:50 -04:00
Dillon Beliveau	30ddd2d579	handle element in VADD	2020-09-12 13:56:07 -04:00
Dillon Beliveau	b395a39224	handle element in VCH	2020-09-12 13:55:11 -04:00
Dillon Beliveau	f7244af6f0	remove some element != 0 checks where handled	2020-09-12 13:55:01 -04:00
Dillon Beliveau	92c6559472	add element != 0 checks everywhere	2020-09-12 13:51:34 -04:00
Dillon Beliveau	cae62af7a0	vte in VNXOR	2020-09-12 13:46:33 -04:00
Dillon Beliveau	36475bc68f	VNE	2020-09-12 13:46:20 -04:00
Dillon Beliveau	f9ee9952d6	VEQ	2020-09-12 13:39:22 -04:00
Dillon Beliveau	d3df05f0f0	vte-related macros	2020-09-12 13:39:15 -04:00
Dillon Beliveau	9354545c5c	rsp XORI	2020-09-12 13:18:05 -04:00
Dillon Beliveau	62ecc3318d	use VTE in VCL	2020-09-12 13:17:38 -04:00
Dillon Beliveau	192ae48fc4	unimplemented macro requires semicolon	2020-09-12 13:07:25 -04:00
Dillon Beliveau	a0e235adbc	fix STV	2020-09-12 09:36:51 -04:00
Dillon Beliveau	0e0a89b520	cleanup RSP test output	2020-09-12 08:48:26 -04:00
Dillon Beliveau	8dabc969e2	fix LTV	2020-09-12 08:48:17 -04:00
Dillon Beliveau	15d4026774	fix VMACU	2020-09-07 20:47:59 -04:00
Dillon Beliveau	06b9e5a810	VMULQ check for zero element	2020-09-07 20:39:04 -04:00
Dillon Beliveau	d952071807	fix VMULU	2020-09-07 20:38:42 -04:00
Dillon Beliveau	f1d90f31e3	fix several multiplies	2020-09-07 20:31:09 -04:00
Dillon Beliveau	5282675cac	fix VMACF	2020-09-07 19:34:44 -04:00
Dillon Beliveau	e85f6303f7	fix VMULF	2020-09-07 19:33:21 -04:00
Dillon Beliveau	f144a83a01	element selector in multiplies	2020-09-07 19:04:12 -04:00
Dillon Beliveau	531be9d51c	fix clamping in VMADN	2020-09-07 16:02:30 -04:00
Dillon Beliveau	10a5bfde7f	Merge branch 'master' of github.com:Dillonb/n64 into master	2020-09-07 14:55:16 -04:00
Dillon Beliveau	74afbafe25	all log macros need semicolons	2020-09-07 14:07:11 -04:00
Dillon Beliveau	78aa785093	rsp tests display all log differences before exiting	2020-09-06 11:09:04 -04:00
Dillon Beliveau	5464d9e027	same fix for vrcp	2020-09-05 16:18:38 -04:00