Dillon Beliveau
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0c203d4b95
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logdie should still work when logging disabled
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2020-10-04 12:17:30 -04:00 |
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Dillon Beliveau
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8f8827f91e
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stub stuff for parallel-rdp and vulkan
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2020-10-04 12:17:05 -04:00 |
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Dillon Beliveau
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22cbec8a84
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newest commit of my parallel-rdp fork
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2020-10-03 21:32:45 -04:00 |
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Dillon Beliveau
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ec7143c93c
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Merge branch 'master' into parallel-rdp
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2020-10-03 21:28:57 -04:00 |
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Dillon Beliveau
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02577b56c1
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rearrange, inline
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2020-10-03 21:28:32 -04:00 |
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Dillon Beliveau
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4bf05ededf
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use pointers, inline
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2020-10-03 20:55:03 -04:00 |
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Dillon Beliveau
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2ab1edde34
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since the RSP's PC is always >>2 before it's used, just store it as its value >>2
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2020-10-03 20:15:55 -04:00 |
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Dillon Beliveau
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f41bbef60b
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don't even call RSP if it's halted
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2020-10-03 19:49:08 -04:00 |
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Dillon Beliveau
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50021b5a23
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hopefully slightly faster RSP / CPU timing sync
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2020-10-03 19:46:39 -04:00 |
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Dillon Beliveau
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bc8edfb9df
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comment out tests failing because of unimplemented instructions
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2020-10-03 18:20:08 -04:00 |
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Dillon Beliveau
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8b6bb653e5
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parallel-rdp
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2020-10-03 18:01:10 -04:00 |
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Dillon Beliveau
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0aece987ba
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stub reading from CART_2_1
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2020-10-03 17:01:35 -04:00 |
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Dillon Beliveau
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d5c50e9a8e
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stub mempack read
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2020-10-03 16:56:07 -04:00 |
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Dillon Beliveau
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5e21e9a46a
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flush codecache when full
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2020-10-03 16:55:56 -04:00 |
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Dillon Beliveau
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7bd5dc2054
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Merge branch 'master' of github.com:Dillonb/n64 into master
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2020-10-03 16:02:49 -04:00 |
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Dillon Beliveau
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454d7710d9
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Update README.md
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2020-10-03 16:02:23 -04:00 |
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Dillon Beliveau
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a284229033
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vxor use vte
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2020-10-03 15:07:49 -04:00 |
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Dillon Beliveau
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e655109e80
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some logwarns to loginfo
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2020-10-03 14:26:14 -04:00 |
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Dillon Beliveau
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088c275208
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remove an unnecessary check on register access
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2020-10-03 14:21:50 -04:00 |
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Dillon Beliveau
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72d7a7cf6b
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don't redefine
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2020-10-03 14:20:50 -04:00 |
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Dillon Beliveau
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e93f2c4d46
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RSP cannot read/write DWORDs
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2020-10-03 14:20:43 -04:00 |
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Dillon Beliveau
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d00106d935
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fix build when log enabled
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2020-10-03 14:20:31 -04:00 |
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Dillon Beliveau
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5d7517304b
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Merge pull request #3 from Dillonb/dynarec
Dynarec
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2020-10-03 13:39:40 -04:00 |
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Dillon Beliveau
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41df53bf49
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cleanup logs when enabled
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2020-10-02 12:19:44 -04:00 |
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Dillon Beliveau
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5808fee06b
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speed up addi
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2020-10-02 12:13:58 -04:00 |
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Dillon Beliveau
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b7036f3cdd
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speed up BEQ
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2020-10-02 12:02:09 -04:00 |
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Dillon Beliveau
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edbf24dd7a
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perform all RSP steps at once without repeatedly calling
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2020-10-02 10:56:36 -04:00 |
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Dillon Beliveau
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5a3db7ab61
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comment
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2020-10-02 10:38:21 -04:00 |
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Dillon Beliveau
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eafa8d72bc
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better error messages
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2020-10-02 10:36:14 -04:00 |
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Dillon Beliveau
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67e94b3eb7
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return block length from run function, remove unused block properties
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2020-10-02 10:27:23 -04:00 |
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Dillon Beliveau
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6e3779e19e
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print statements behind ifdef
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2020-10-02 09:53:01 -04:00 |
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Dillon Beliveau
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6111f9dc9f
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stray chunk of code that shouldn't be there
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2020-10-02 02:11:51 -04:00 |
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Dillon Beliveau
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83503bc112
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inline pre_instruction in asm
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2020-10-02 02:11:23 -04:00 |
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Dillon Beliveau
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8fef998a84
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remove print statements. fix a common edge case, break a much rarer one.
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2020-10-02 01:15:27 -04:00 |
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Dillon Beliveau
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f50a4e5595
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exit block early on CP1 unusable exceptions
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2020-10-01 22:08:09 -04:00 |
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Dillon Beliveau
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4b8739f3ce
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don't save rax, move cpu_state type to top of file
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2020-10-01 22:06:52 -04:00 |
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Dillon Beliveau
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d4f9b26142
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compile cp1
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2020-10-01 20:52:10 -04:00 |
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Dillon Beliveau
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ca8425b160
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oops
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2020-10-01 19:53:21 -04:00 |
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Dillon Beliveau
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ed2f60806a
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branches don't end blocks
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2020-10-01 19:32:34 -04:00 |
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Dillon Beliveau
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8638091126
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regimm, switch terminology to compile from emit
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2020-10-01 16:31:24 -04:00 |
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Dillon Beliveau
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15bfc6c6d3
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delay slots/branch likely instructions should be working now
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2020-10-01 16:18:07 -04:00 |
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Dillon Beliveau
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f6212a9d15
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keep track of the number of blocks run
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2020-10-01 13:05:31 -04:00 |
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Dillon Beliveau
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d7faa6ba8c
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make sure we're at the right PC
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2020-10-01 13:05:19 -04:00 |
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Dillon Beliveau
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a1f0eabbd6
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emit special instructions
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2020-10-01 12:36:10 -04:00 |
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Dillon Beliveau
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e7c85e344a
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emitters return their category, need to emit the delay slot for branch instrs
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2020-10-01 12:25:38 -04:00 |
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Dillon Beliveau
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0fc6591fa9
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less redundant log messages
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2020-10-01 12:01:03 -04:00 |
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Dillon Beliveau
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48a9510744
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builds on MacOS
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2020-10-01 10:15:00 -04:00 |
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Dillon Beliveau
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d83cb1f1c1
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attempting to fix blocks
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2020-10-01 09:30:41 -04:00 |
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Dillon Beliveau
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cbbed8da66
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emit cp0 instructions
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2020-09-29 20:25:21 -04:00 |
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Dillon Beliveau
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39e2435550
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compile all basic instructions
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2020-09-29 20:20:16 -04:00 |
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