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1910 commits 16 branches 0 tags 17 MiB
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Author SHA1 Message Date
Dillon Beliveau
59516b04de more vulkan init progress 2020-10-04 17:14:44 -04:00
Dillon Beliveau
857f6d1ad2 vulkan extensions 2020-10-04 13:01:06 -04:00
Dillon Beliveau
545d2f93e9 glad needs loaders 2020-10-04 12:55:07 -04:00
Dillon Beliveau
e586e1fbcb switch to Glad 2 2020-10-04 12:34:48 -04:00
Dillon Beliveau
0c203d4b95 logdie should still work when logging disabled 2020-10-04 12:17:30 -04:00
Dillon Beliveau
8f8827f91e stub stuff for parallel-rdp and vulkan 2020-10-04 12:17:05 -04:00
Dillon Beliveau
22cbec8a84 newest commit of my parallel-rdp fork 2020-10-03 21:32:45 -04:00
Dillon Beliveau
ec7143c93c Merge branch 'master' into parallel-rdp 2020-10-03 21:28:57 -04:00
Dillon Beliveau
02577b56c1 rearrange, inline 2020-10-03 21:28:32 -04:00
Dillon Beliveau
4bf05ededf use pointers, inline 2020-10-03 20:55:03 -04:00
Dillon Beliveau
2ab1edde34 since the RSP's PC is always >>2 before it's used, just store it as its value >>2 2020-10-03 20:15:55 -04:00
Dillon Beliveau
f41bbef60b don't even call RSP if it's halted 2020-10-03 19:49:08 -04:00
Dillon Beliveau
50021b5a23 hopefully slightly faster RSP / CPU timing sync 2020-10-03 19:46:39 -04:00
Dillon Beliveau
bc8edfb9df comment out tests failing because of unimplemented instructions 2020-10-03 18:20:08 -04:00
Dillon Beliveau
8b6bb653e5 parallel-rdp 2020-10-03 18:01:10 -04:00
Dillon Beliveau
0aece987ba stub reading from CART_2_1 2020-10-03 17:01:35 -04:00
Dillon Beliveau
d5c50e9a8e stub mempack read 2020-10-03 16:56:07 -04:00
Dillon Beliveau
5e21e9a46a flush codecache when full 2020-10-03 16:55:56 -04:00
Dillon Beliveau
7bd5dc2054 Merge branch 'master' of github.com:Dillonb/n64 into master 2020-10-03 16:02:49 -04:00
Dillon Beliveau
454d7710d9
Update README.md 2020-10-03 16:02:23 -04:00
Dillon Beliveau
a284229033 vxor use vte 2020-10-03 15:07:49 -04:00
Dillon Beliveau
e655109e80 some logwarns to loginfo 2020-10-03 14:26:14 -04:00
Dillon Beliveau
088c275208 remove an unnecessary check on register access 2020-10-03 14:21:50 -04:00
Dillon Beliveau
72d7a7cf6b don't redefine 2020-10-03 14:20:50 -04:00
Dillon Beliveau
e93f2c4d46 RSP cannot read/write DWORDs 2020-10-03 14:20:43 -04:00
Dillon Beliveau
d00106d935 fix build when log enabled 2020-10-03 14:20:31 -04:00
Dillon Beliveau
5d7517304b
Merge pull request #3 from Dillonb/dynarec 
Dynarec
 2020-10-03 13:39:40 -04:00
Dillon Beliveau
41df53bf49 cleanup logs when enabled 2020-10-02 12:19:44 -04:00
Dillon Beliveau
5808fee06b speed up addi 2020-10-02 12:13:58 -04:00
Dillon Beliveau
b7036f3cdd speed up BEQ 2020-10-02 12:02:09 -04:00
Dillon Beliveau
edbf24dd7a perform all RSP steps at once without repeatedly calling 2020-10-02 10:56:36 -04:00
Dillon Beliveau
5a3db7ab61 comment 2020-10-02 10:38:21 -04:00
Dillon Beliveau
eafa8d72bc better error messages 2020-10-02 10:36:14 -04:00
Dillon Beliveau
67e94b3eb7 return block length from run function, remove unused block properties 2020-10-02 10:27:23 -04:00
Dillon Beliveau
6e3779e19e print statements behind ifdef 2020-10-02 09:53:01 -04:00
Dillon Beliveau
6111f9dc9f stray chunk of code that shouldn't be there 2020-10-02 02:11:51 -04:00
Dillon Beliveau
83503bc112 inline pre_instruction in asm 2020-10-02 02:11:23 -04:00
Dillon Beliveau
8fef998a84 remove print statements. fix a common edge case, break a much rarer one. 2020-10-02 01:15:27 -04:00
Dillon Beliveau
f50a4e5595 exit block early on CP1 unusable exceptions 2020-10-01 22:08:09 -04:00
Dillon Beliveau
4b8739f3ce don't save rax, move cpu_state type to top of file 2020-10-01 22:06:52 -04:00
Dillon Beliveau
d4f9b26142 compile cp1 2020-10-01 20:52:10 -04:00
Dillon Beliveau
ca8425b160 oops 2020-10-01 19:53:21 -04:00
Dillon Beliveau
ed2f60806a branches don't end blocks 2020-10-01 19:32:34 -04:00
Dillon Beliveau
8638091126 regimm, switch terminology to compile from emit 2020-10-01 16:31:24 -04:00
Dillon Beliveau
15bfc6c6d3 delay slots/branch likely instructions should be working now 2020-10-01 16:18:07 -04:00
Dillon Beliveau
f6212a9d15 keep track of the number of blocks run 2020-10-01 13:05:31 -04:00
Dillon Beliveau
d7faa6ba8c make sure we're at the right PC 2020-10-01 13:05:19 -04:00
Dillon Beliveau
a1f0eabbd6 emit special instructions 2020-10-01 12:36:10 -04:00
Dillon Beliveau
e7c85e344a emitters return their category, need to emit the delay slot for branch instrs 2020-10-01 12:25:38 -04:00
Dillon Beliveau
0fc6591fa9 less redundant log messages 2020-10-01 12:01:03 -04:00