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Author SHA1 Message Date
Dillon Beliveau
9ebc767db3 optimize host_emit_mov_mem_reg to use an offset into N64CPU if possible 2023-02-11 11:15:06 -08:00
Dillon Beliveau
3a4b0b6d0e
Move setup-nasm action to top level 2023-02-06 09:41:36 -08:00
Dillon Beliveau
77431e74dc
Install nasm in github actions 2023-02-06 09:36:28 -08:00
Dillon Beliveau
67d777c78f AND two variable values 2023-02-05 19:11:08 -08:00
Dillon Beliveau
0f1feb3a40 flush registers when block exited early 2023-02-05 19:01:25 -08:00
Dillon Beliveau
c99533ee8d finish exit block early test, broken implementation 2023-02-05 18:02:43 -08:00
Dillon Beliveau
80581dd926 compiled not, start working on likely branches, start setting up unit tests for dynarec 2023-02-05 17:18:06 -08:00
Dillon Beliveau
b59d55c80b sltu, and, or, nop cache 2023-02-05 15:28:22 -08:00
Dillon Beliveau
b9f56d6820 Logging updates 2023-02-05 15:10:43 -08:00
Dillon Beliveau
c230cff119 compiled or, not, mtc0, sanitizers not passed to nasm, reserve r12 for cpu pointer, flush regs as early as possible, const shift, 2023-02-05 15:06:36 -08:00
Dillon Beliveau
397beebe00 quiet down logs 2023-02-05 02:34:23 -08:00
Dillon Beliveau
e4c37fca2c s8 -> fp 2023-02-05 02:18:53 -08:00
Dillon Beliveau
26fea58bb6 srl, lb, bgtz, addi 2023-02-05 02:18:45 -08:00
Dillon Beliveau
9865dbc16a jit crashes on TLB MISS PC for now 2023-02-05 02:17:00 -08:00
Dillon Beliveau
b6d87f0412 sh, sd, lbu, lh, j, jal, addu, slt + propagate constants for check condition & set_cond_exit_pc 2023-02-05 00:32:51 -08:00
Dillon Beliveau
1ef1638734 beq 2023-02-05 00:02:20 -08:00
Dillon Beliveau
7374781840 addiu 2023-02-04 23:51:16 -08:00
Dillon Beliveau
9d1372058a fix block->run call 2023-02-04 23:50:31 -08:00
Dillon Beliveau
a19dd6c08d fix register allocation 2023-02-04 23:50:04 -08:00
Dillon Beliveau
f51bd073e6 fix stack alignment 2023-02-04 23:49:47 -08:00
Dillon Beliveau
06a7e55d4c Crash when unable to match address to region 2023-02-04 22:50:36 -08:00
Dillon Beliveau
027f87eebc Wrong type 2023-02-04 22:48:45 -08:00
Dillon Beliveau
c9e2318e88 sll, jalr, add 2023-02-04 21:23:29 -08:00
Dillon Beliveau
ecba2a94ac lhu, ld, jr 2023-02-04 19:55:38 -08:00
Dillon Beliveau
d4ddbd6378 Better (but very inefficient) register allocation by calculating lifetimes 2023-02-04 17:19:53 -08:00
Dillon Beliveau
96e18a966d Don't use RSP for register allocation 2023-02-04 17:17:16 -08:00
Dillon Beliveau
ce0d291596 compile ADD & TLB_LOOKUP 2023-02-04 17:16:24 -08:00
Dillon Beliveau
f4cf4ea39a Load guest reg set by another block 2023-02-04 16:15:25 -08:00
Dillon Beliveau
93a11f4252 flush guest regs at the end of the block 2023-02-04 16:01:39 -08:00
Dillon Beliveau
a995a900d6 temporary "dispatcher" in ASM - wrap block thunks in an ASM function 2023-02-04 15:25:43 -08:00
Dillon Beliveau
697434a2f4 check condition, set exit pc 2023-02-04 14:05:26 -08:00
Dillon Beliveau
0c6ccdd3ce compile IR_AND 2023-01-29 16:17:28 -08:00
Dillon Beliveau
b791cd691a begin work on x86_64 emitter 2023-01-29 16:00:21 -08:00
Dillon Beliveau
70ece93da6 TLB lookup IR instruction 2023-01-29 14:22:04 -08:00
Dillon Beliveau
b640c14287 asm_emitter -> v1_emitter 2023-01-29 14:20:30 -08:00
Dillon Beliveau
31b2edb26a minimum viable register allocation 2023-01-29 12:56:23 -08:00
Dillon Beliveau
0581de8f44 Only print when actually allocating a guest reg 2023-01-29 11:15:01 -08:00
Dillon Beliveau
e68656f665 Document functions in target_platform, add is_valid_immediate() 2023-01-29 11:10:08 -08:00
Dillon Beliveau
b3d8b285c3 Rework IR storage to use a linked list and pointers instead of indices 2023-01-29 11:08:47 -08:00
Dillon Beliveau
87d51c5c47 remove unused 2023-01-28 16:01:29 -08:00
Dillon Beliveau
3f3ef2622e Enable -Werror=switch 2023-01-28 16:01:17 -08:00
Dillon Beliveau
d343bb7370 shrink constants 2023-01-28 14:44:54 -08:00
Dillon Beliveau
392fa1379c fix for values mapped to registers, add todo comment 2023-01-28 14:13:36 -08:00
Dillon Beliveau
6f3bacb310 constant propagation and dead code elimination 2023-01-28 13:31:07 -08:00
Dillon Beliveau
1613bd46aa helpers for ir_emit_set_constant, documentation comments 2023-01-28 12:27:37 -08:00
Dillon Beliveau
b372cff267 abstract away common branch code 2023-01-28 12:15:29 -08:00
Dillon Beliveau
30b650ec19 don't print v%d= where it doesn't make sense 2023-01-28 12:07:20 -08:00
Dillon Beliveau
7a0f66431c More IR instructions, handle branches 2023-01-28 11:58:35 -08:00
Dillon Beliveau
aa3b9e10d7 print IR as string 2023-01-22 17:15:12 -08:00
Dillon Beliveau
6a224a1639 don't load extra zero constants 2023-01-22 15:26:16 -08:00