54 commits

Author	SHA1	Message	Date
Simone Coco	9ebc6a101d	Correct default COP0.Status value for PIF HLE (#26)	2022-06-14 14:19:19 -07:00
Dillon Beliveau	7727eb45bf	Remove duplicate	2021-06-07 22:56:40 -04:00
Dillon Beliveau	9130d01736	Hyphens	2021-04-26 09:00:25 -04:00
Dillon Beliveau	0fcb392488	Fix table header	2021-04-26 08:56:46 -04:00
Dillon Beliveau	54221a54b4	Rogue Squadron to issues log	2021-04-25 17:21:07 -04:00
Dillon Beliveau	2af5fa8c19	Banjo-Tooie and Banjo-Kazooie to issues log	2021-04-24 20:55:27 -04:00
Dillon Beliveau	25202b4721	Paper Mario to issues log	2021-04-18 17:18:29 -04:00
Dillon Beliveau	c7ae82acaf	use COPx naming convention in docs	2021-04-17 09:04:06 -04:00
Dillon Beliveau	72f77a2a04	Update boot_process.rst	2021-04-12 10:12:11 -04:00
Dillon Beliveau	bf300e2e1f	Exception documentation	2021-04-11 14:33:42 -04:00
Dillon Beliveau	abbfb046a2	fix wording a little	2021-04-11 13:20:34 -04:00
Dillon Beliveau	fd47bed4c4	more clearly mark when we switch to talking about the CPU internals	2021-04-11 13:17:12 -04:00
Dillon Beliveau	6051b8fecb	interrupts	2021-04-11 13:13:52 -04:00
Dillon Beliveau	8a83990069	Document more CPU stuff	2021-04-11 12:10:30 -04:00
Dillon Beliveau	7057005539	update memory map with locations of N64DD stuff	2021-04-11 11:49:02 -04:00
Dillon Beliveau	42e3a998c2	TODOs for rest of VI registers	2021-04-11 11:32:53 -04:00
Dillon Beliveau	0b0444845b	document VI_STATUS_REG	2021-04-11 11:06:59 -04:00
Dillon Beliveau	a58359160d	F-Zero X to issues log	2021-04-10 10:10:12 -04:00
Dillon Beliveau	deb45e0d3e	Update memory_map.rst	2021-02-17 10:12:10 -05:00
Dillon Beliveau	9fd323d932	Update issues_log.rst	2021-02-15 17:30:37 -05:00
Dillon Beliveau	669154799a	Update issues_log.rst	2021-02-15 17:29:30 -05:00
Mihalache Mihai	8a1c8943b4	Update memory_map.rst ... Fixed a typo	2021-02-11 22:03:59 +02:00
Dillon Beliveau	92bc5b6be4	per instruction, not per cycle	2021-02-06 14:47:31 -05:00
wheremyfoodat	c29ab936d7	Fixed sign extension of initial $t3 val	2021-02-06 14:07:48 +02:00
wheremyfoodat	3a8e77c5fa	Update PIF doc	2021-02-06 13:32:57 +02:00
Dillon Beliveau	1c9bb1a54c	missed some zeroes	2021-01-18 14:08:44 -05:00
Dillon Beliveau	1df95a9a7f	Corrections and clarity for boot process doc	2021-01-16 11:09:22 -05:00
Dillon Beliveau	55e0f59148	Small issues log	2021-01-08 21:34:06 -05:00
Dillon Beliveau	fb1b99e045	Use groundwork theme for RTD	2021-01-04 19:54:42 -05:00
Dillon Beliveau	1344530614	CP0 registers docs updates	2020-12-28 18:11:16 -05:00
Dillon Beliveau	2c25314dab	fix MI_VERSION_REG	2020-12-28 00:53:59 -05:00
Dillon Beliveau	f5303cb5a8	combine cells	2020-12-22 20:29:44 -05:00
Dillon Beliveau	11bba27c24	change theme and formatting of some tables	2020-12-22 19:38:36 -05:00
Dillon Beliveau	d9cc6edc9d	Every MIPS interface register documented	2020-12-22 00:53:16 -05:00
Dillon Beliveau	5f72ce7461	more MI docs	2020-12-22 00:42:41 -05:00
Dillon Beliveau	458ece5fe9	document one MI register	2020-12-22 00:14:02 -05:00
Dillon Beliveau	a80c4b1bac	Typo	2020-10-30 23:12:25 -04:00
Dillon Beliveau	a961810250	Program counter is 64 bits	2020-10-27 12:51:42 -04:00
Dillon Beliveau	70f60424bd	quick updates	2020-10-26 22:26:29 -04:00
Dillon Beliveau	c4460d1a2f	document Count/Compare	2020-10-26 22:22:35 -04:00
Dillon Beliveau	8464e5ee18	document random registers	2020-10-26 22:18:54 -04:00
Dillon Beliveau	2ba9cdc36f	link bootcode analysis	2020-10-26 22:18:41 -04:00
Dillon Beliveau	0cd0fb16b9	typo	2020-10-26 22:01:42 -04:00
Dillon Beliveau	bae2c2a20d	sort remaining CP0 registers	2020-10-26 22:00:34 -04:00
Dillon Beliveau	30890465f4	document boot process, list CPU and CP0 registers	2020-10-26 21:43:45 -04:00
Dillon Beliveau	34b0edf119	Docs are WIP	2020-10-24 17:55:51 -04:00
Dillon Beliveau	dc44fe8446	Descriptions of more memory regions	2020-10-24 11:31:00 -04:00
Dillon Beliveau	457b2d9f12	Update memory_map.rst	2020-10-22 10:38:25 -04:00
Dillon Beliveau	0dcd42ca38	Update index.rst	2020-10-22 09:23:40 -04:00
Dillon Beliveau	abb6995b64	switch to haiku theme for sphinx	2020-10-21 22:23:14 -04:00