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Author SHA1 Message Date
Dillon Beliveau
8fae77d346 mkdir dynarec_v2_tests before building file into it 2023-03-04 17:46:50 -08:00
Dillon Beliveau
41bd14bd6e print cwd when test_dynarec_v2 fails to open code file 2023-03-04 17:28:09 -08:00
Dillon Beliveau
668b843f3e dadd, daddu, dsub, dsubu, spilling fixes 2023-03-04 16:46:14 -08:00
Dillon Beliveau
18f37d593b spilling fixes 2023-03-04 16:31:06 -08:00
Dillon Beliveau
b6d3f50bbc trunc double->word 2023-03-04 16:07:46 -08:00
Dillon Beliveau
1c48d6f5ab blezl, float lt compare, bc1t, bc1f, bc1fl 2023-03-04 16:02:08 -08:00
Dillon Beliveau
567da2fd81 handle spilled cond reg 2023-03-04 15:55:41 -08:00
Dillon Beliveau
7cf1094afb mult 2023-03-04 15:55:32 -08:00
Dillon Beliveau
a3705f4186 subtraction with reg - imm 2023-03-04 15:38:23 -08:00
Dillon Beliveau
98aad3f509 fpu mov 2023-03-04 15:26:02 -08:00
Dillon Beliveau
29d5a5ef74 log block size in all cases 2023-03-04 15:25:31 -08:00
Dillon Beliveau
bf27db8ab2 fix NOT constant propagation, improve constant shrinking 2023-03-04 15:25:18 -08:00
Dillon Beliveau
baa75790ae mult u32 reg reg 2023-03-04 14:38:19 -08:00
Dillon Beliveau
615c4adb84 better calculation of what instructions to put into a block 2023-03-04 14:31:06 -08:00
Dillon Beliveau
fd8539962a trunc 2023-03-04 14:27:47 -08:00
Dillon Beliveau
9c4a97aa07 a few minor fixes 2023-03-04 14:27:28 -08:00
Dillon Beliveau
0d3dc5bb3f mfc1 2023-03-01 00:49:41 -08:00
Dillon Beliveau
7fa0c7019f convert float types with different modes 2023-03-01 00:44:51 -08:00
Dillon Beliveau
f268d956bf float cmp, sub 2023-03-01 00:32:42 -08:00
Dillon Beliveau
06e58f7089 fix loading FGRs at the beginning of blocks 2023-03-01 00:32:22 -08:00
Dillon Beliveau
ba742d41da compile float addition 2023-02-28 23:16:37 -08:00
Dillon Beliveau
2379544b5f float constants 2023-02-28 23:11:16 -08:00
Dillon Beliveau
6d55d6ee8a more stubs, implement float divides 2023-02-28 22:36:10 -08:00
Dillon Beliveau
7322b56a9d determine type 2023-02-28 22:18:52 -08:00
Dillon Beliveau
8a6b355cbf fixes, stub float subtraction 2023-02-28 22:17:50 -08:00
Dillon Beliveau
f4a02719e6 stub ir_float_check_condition, implement bc1tl 2023-02-28 22:04:18 -08:00
Dillon Beliveau
602b15e914 stub floating point divides and adds 2023-02-27 00:23:54 -08:00
Dillon Beliveau
0cc0b890e6 swc1, fix fgrs being reused for smaller values, emit cvt instructions 2023-02-26 18:02:13 -08:00
Dillon Beliveau
819659e510 LDC1, SDC1 2023-02-26 15:36:04 -08:00
Dillon Beliveau
5d155dbfb2 fix bug in register flushing 2023-02-26 15:35:46 -08:00
Dillon Beliveau
5ae2b28272 lwc1, cp1 cvt instructions 2023-02-26 15:06:51 -08:00
Dillon Beliveau
fd39ae898d handle consts in mov_reg_type 2023-02-26 10:40:57 -08:00
Dillon Beliveau
13fb1d6edb remove printfs 2023-02-25 18:36:20 -08:00
Dillon Beliveau
11dbb2be39 print_ir_block in header 2023-02-25 17:50:34 -08:00
Dillon Beliveau
380a9a1977 stub FPU IR emitters 2023-02-25 17:48:59 -08:00
Dillon Beliveau
4b2d2118f1 nicer output formatting 2023-02-25 17:48:23 -08:00
Dillon Beliveau
71d406fd8c fix warnings 2023-02-25 17:48:10 -08:00
Dillon Beliveau
94cf6af256 flush FPU registers 2023-02-25 17:30:29 -08:00
Dillon Beliveau
029996c025 fix test 2023-02-24 17:52:29 -08:00
Dillon Beliveau
b442ea894a allocate FPU registers 2023-02-24 17:45:59 -08:00
Dillon Beliveau
8678084991 remove logfatal 2023-02-22 00:17:58 -08:00
Dillon Beliveau
40bcfe6257 oops 2023-02-20 16:54:26 -08:00
Dillon Beliveau
e69edd528c macro for blockcache outer index 2023-02-20 16:37:24 -08:00
Dillon Beliveau
81de6a8638 fix coprocessor instruction decoding 2023-02-20 16:21:25 -08:00
Dillon Beliveau
950c557c19 print IR when difference found 2023-02-20 15:51:52 -08:00
Dillon Beliveau
c9b5ac6296 refactor interpreter to allow running the CPU for more than a single cycle at a time 2023-02-20 15:33:04 -08:00
Dillon Beliveau
5c3cd84b5e timing slightly more accurate in n64_system_step 2023-02-20 13:14:39 -08:00
Dillon Beliveau
5034d33fd3 ldl, ldr 2023-02-20 03:20:43 -08:00
Dillon Beliveau
759f633c0f don't expand notted consts 2023-02-20 02:47:08 -08:00
Dillon Beliveau
317b701f28 swl, swr, empty emitters for ldl, ldr, sdl, sdr 2023-02-20 02:46:06 -08:00