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Author	SHA1	Message	Date
Dillon Beliveau	d32d9c49ad	minor fix, expand on comment	2023-08-25 19:56:07 -07:00
Dillon Beliveau	2b590aeb9a	Include vulkan_headers.hpp first	2023-08-24 20:27:05 -07:00
Dillon Beliveau	f35a4faf15	Merge branch 'dynarec_v2'	2023-08-24 00:12:55 -07:00
Dillon Beliveau	2d774afecb	Merge pull request #38 from Dillonb/dynarec_v2 ... Dynarec v2	2023-08-24 00:12:14 -07:00
Dillon Beliveau	4a229161ac	make this a warning	2023-08-23 23:58:58 -07:00
Dillon Beliveau	0b9ff6bb0c	register spilling rework	2023-08-23 23:21:57 -07:00
Dillon Beliveau	360c2e64be	prep for register spilling rework	2023-08-23 22:34:30 -07:00
Dillon Beliveau	02e3c5be0c	don't recalculate sysconfig every time	2023-08-23 20:52:22 -07:00
Dillon Beliveau	6a8141ec27	fix unlocking framerate on windows	2023-08-23 20:51:04 -07:00
Dillon Beliveau	dd5e5d4bea	split rsp link stage	2023-08-22 01:26:59 -07:00
Dillon Beliveau	6247ab3ee6	Merge branch 'master' into dynarec_v2	2023-08-22 01:26:06 -07:00
Dillon Beliveau	e65c6c553f	Update parallel-rdp	2023-08-21 21:47:10 -07:00
Dillon Beliveau	1de8d567e8	Error check creating SDL resources	2023-08-20 05:36:55 +00:00
Dillon Beliveau	314d4c4f4d	Only use SSE if available	2023-08-20 05:36:28 +00:00
Dillon Beliveau	cb6e800dad	send linux debug logs to stderr	2023-08-08 23:44:06 -07:00
Dillon Beliveau	cccc33fd1b	fix build when building without SIMD	2023-08-05 12:25:23 -07:00
Dillon Beliveau	ec46e808b6	consistent naming	2023-08-01 22:40:13 -07:00
Dillon Beliveau	cc12fd927a	remove unused	2023-08-01 22:40:04 -07:00
Dillon Beliveau	ebe665cb76	Merge branch 'master' into dynarec_v2	2023-07-29 14:24:41 -07:00
Dillon Beliveau	3abd96f15a	remove unused values	2023-07-29 14:23:35 -07:00
Dillon Beliveau	14acafda6b	inline, add parens to silence warning	2023-07-29 14:22:42 -07:00
Dillon Beliveau	6e8652d79c	reorder operations in sc and scd to match the interpreter	2023-07-23 17:35:09 -07:00
Dillon Beliveau	5cc3b49e3a	check llbit in dynarec compare tool	2023-07-23 17:26:15 -07:00
Dillon Beliveau	0f48b25fea	make the block's virtual address a compile time constant	2023-07-23 16:36:30 -07:00
Dillon Beliveau	aab8bba894	disassemble guest code based on virtual address, not physical	2023-07-22 22:07:05 -07:00
Dillon Beliveau	1f0636e58e	random number generation should be deterministic for both parent and child in dynarec compare tool	2023-07-22 22:06:54 -07:00
Dillon Beliveau	c061b67c32	fix tlb exceptions when tlb_lookup destination reg is spilled	2023-07-22 22:06:30 -07:00
Dillon Beliveau	0a7311fd0f	don't shrink constants down to u32 if the sign bit is set	2023-07-22 22:05:49 -07:00
Dillon Beliveau	5bc12895b3	fix format string	2023-07-22 22:05:37 -07:00
Dillon Beliveau	dae333377b	Merge branch 'master' into dynarec_v2	2023-07-22 18:22:55 -07:00
Dillon Beliveau	38dafa90a5	Fix LL	2023-07-22 17:04:55 -07:00
Dillon Beliveau	fe8b0a59b6	support for logging CPU state	2023-07-22 17:04:47 -07:00
Dillon Beliveau	75959e5f1b	print constant type	2023-07-22 17:04:08 -07:00
Dillon Beliveau	0ce1792f34	fix JIT TLB exceptions	2023-07-22 17:03:43 -07:00
Dillon Beliveau	985c615249	fix count reg in matchjit interpreter	2023-07-22 15:06:19 -07:00
Dillon Beliveau	00c74a7329	Awful hack to fix CP0 register names in disassembly	2023-07-22 14:50:05 -07:00
Dillon Beliveau	a0bbefa4d9	software mode in compare tool	2023-07-22 14:02:02 -07:00
Dillon Beliveau	56bb6d0dac	check window initialization	2023-07-16 23:38:35 -07:00
Dillon Beliveau	cf86d0d531	fix more format specifiers	2023-07-16 22:55:22 -07:00
Dillon Beliveau	131ae1f2c5	replace more printf format specifiers with macro	2023-07-16 18:54:47 -07:00
Dillon Beliveau	09263a71c7	Merge branch 'master' into dynarec_v2	2023-07-16 18:52:51 -07:00
Dillon Beliveau	744d8ed655	use macros for format strings	2023-07-16 18:45:48 -07:00
Dillon Beliveau	7d556f46a9	add extra warning	2023-07-16 15:48:50 -07:00
Dillon Beliveau	bc2cdc1707	fix an invalid block length bug	2023-07-16 15:48:45 -07:00
Dillon Beliveau	f9a3fd6021	RDHWR	2023-07-16 14:33:09 -07:00
Dillon Beliveau	8707054bd9	tlb exceptions improvements	2023-07-16 14:29:22 -07:00
Dillon Beliveau	b74f1f11b9	tlb exceptions, wip	2023-07-15 15:33:24 -07:00
Dillon Beliveau	5a1876d46a	logtester verify cp0 cause and mi intr	2023-07-15 12:49:55 -07:00
Dillon Beliveau	22ce68e83d	interrupt timing issues	2023-07-15 12:49:45 -07:00
Dillon Beliveau	dc620ea9ef	update interrupts for ip0 and ip1	2023-07-15 11:56:59 -07:00