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Author SHA1 Message Date
Dillon Beliveau
3d6379b258 fix VMUDH 2020-07-20 19:02:22 -04:00
Dillon Beliveau
65c56cec4a pass VMADM 2020-07-20 18:54:29 -04:00
Dillon Beliveau
40098f5d0f use correct settings 2020-07-20 18:44:16 -04:00
Dillon Beliveau
a0f98083f1 fix log line 2020-07-19 17:49:57 -04:00
Dillon Beliveau
e1fcd6e9a1 fix VRCPH 2020-07-19 17:49:05 -04:00
Dillon Beliveau
a25106e31d fix VADD 2020-07-19 17:48:53 -04:00
Dillon Beliveau
f20cd11f3a fix VRCPL 2020-07-19 16:45:44 -04:00
Dillon Beliveau
d00a2d8e63 fix VLT 2020-07-19 16:07:48 -04:00
Dillon Beliveau
5cb8642580 VXOR/VNXOR set the acc as well 2020-07-19 16:00:27 -04:00
Dillon Beliveau
6ec013a332 rewrite VCH 2020-07-19 15:53:29 -04:00
Dillon Beliveau
c471fc0568 dumb typo 2020-07-19 15:40:26 -04:00
Dillon Beliveau
1976f74588 remove pseudocode comments 2020-07-19 14:20:59 -04:00
Dillon Beliveau
0f7ab14192 free(system) 2020-07-19 14:19:10 -04:00
Dillon Beliveau
cbf8bdf7b4 Fixing VCL 2020-07-19 14:19:02 -04:00
Dillon Beliveau
4df35426a7 endianness strikes again 2020-07-19 14:17:57 -04:00
Dillon Beliveau
103d15811a VOR and VNOR set the accumulator too 2020-07-19 13:33:51 -04:00
Dillon Beliveau
36a3a3c380 VAND and VNAND set the accumulator too 2020-07-19 13:33:51 -04:00
Dillon Beliveau
a7fe26cc38 couple more (probably broken) RSP instructions 2020-07-19 13:02:07 -04:00
Dillon Beliveau
647b541a1f VRCPH 2020-07-19 10:49:04 -04:00
Dillon Beliveau
80434c5fde VMUDL 2020-07-18 20:18:41 -04:00
Dillon Beliveau
9911d9637b VCL 2020-07-18 20:11:27 -04:00
Dillon Beliveau
4c493edc34 VCH 2020-07-18 20:11:19 -04:00
Dillon Beliveau
b1adb985e0 VADD 2020-07-18 20:11:05 -04:00
Dillon Beliveau
fda27a3459 fix RSP registers 2020-07-18 20:10:55 -04:00
Dillon Beliveau
4ab59dcb71 this passes now 2020-07-17 23:11:01 -04:00
Dillon Beliveau
ac772772a6 Don't clear RSP state in between subtest runs 2020-07-17 23:07:20 -04:00
Dillon Beliveau
b369d71ff0 these now pass 2020-07-17 00:37:53 -04:00
Dillon Beliveau
46c4ded4ca use correct element 2020-07-17 00:34:30 -04:00
Dillon Beliveau
82d4b279bf Fix VMUDH 2020-07-16 21:28:41 -04:00
Dillon Beliveau
1d2af6cf20 comment out tests that don't pass yet 2020-07-15 21:21:38 -04:00
Dillon Beliveau
1ea21db31e Remove this kinda useless line 2020-07-15 21:21:38 -04:00
Dillon Beliveau
697ed11f35
Update README.md 2020-07-15 14:13:23 -04:00
Dillon Beliveau
77a1f081d0
Update README.md 2020-07-15 14:01:02 -04:00
Dillon Beliveau
70ab74ff85
Create README.md 2020-07-15 13:59:09 -04:00
Dillon Beliveau
ddedacea6f RSP halfword unaligned writes 2020-07-12 23:28:45 -04:00
Dillon Beliveau
d96928ec71 check element == 0. will need to get implemented later 2020-07-12 23:26:36 -04:00
Dillon Beliveau
d3dbabb9bb LLV 2020-07-12 23:00:24 -04:00
Dillon Beliveau
ad18db7b1d VMUDM/VMUDN 2020-07-12 23:00:16 -04:00
Dillon Beliveau
2a2de4ca4d LSV 2020-07-12 23:00:03 -04:00
Dillon Beliveau
8afd5e8047 ADDU and ADDIU are just ADD and ADDI in the RSP 2020-07-12 22:47:56 -04:00
Dillon Beliveau
c46d43f5d3 Make the text output nicer 2020-07-12 22:43:55 -04:00
Dillon Beliveau
716487e001 Housekeeping 2020-07-12 22:05:42 -04:00
Dillon Beliveau
21ef0712a9 fix SQV 2020-07-12 22:02:13 -04:00
Dillon Beliveau
2f9416b0f1 Display expected/actual test output 2020-07-12 22:00:36 -04:00
Dillon Beliveau
f5921e18d4 Still not perfect, but improve LQV and SQV 2020-07-12 21:48:17 -04:00
Dillon Beliveau
fde4ab30e2 This should be a 32 bit conversion 2020-07-12 21:44:41 -04:00
Dillon Beliveau
4cd1827209 TLB WIP 2020-07-12 18:03:27 -04:00
Dillon Beliveau
d098b80806 RSP unaligned word reads 2020-07-12 17:48:58 -04:00
Dillon Beliveau
4a3ec2c185 VAND, VNAND, VNOR, VNXOR, VOR, VXOR 2020-07-12 17:48:37 -04:00
Dillon Beliveau
51f9064f3f Improve LQV and SQV, not perfect yet though 2020-07-12 17:47:53 -04:00