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Author	SHA1	Message	Date
Dillon Beliveau	10a9044e90	endianness, again	2020-07-26 23:22:04 -04:00
Dillon Beliveau	155409cd0a	Merge pull request #1 from Dillonb/tlb-wip ... TLB	2020-07-26 23:20:33 -04:00
Dillon Beliveau	1f31691f97	Merge pull request #2 from Dillonb/gdb-stub ... GDB Stub	2020-07-26 22:31:06 -04:00
Dillon Beliveau	1f5779e09b	breakpoints, -d option, beginnings of a memory map, endianness	2020-07-26 17:51:30 -04:00
Dillon Beliveau	b87c479a67	step fixes, endianness fixes	2020-07-26 12:38:44 -04:00
Dillon Beliveau	114e4c48c8	Initial sorta-working gdb stub	2020-07-25 21:44:49 -04:00
Dillon Beliveau	8c5a150409	not a fatal error, just log it	2020-07-24 19:53:35 -04:00
Dillon Beliveau	f60bb78993	typo	2020-07-24 19:52:02 -04:00
Dillon Beliveau	d2ee10bfb3	tlb fixes, odd pages	2020-07-24 10:44:06 -04:00
Dillon Beliveau	24a35468cf	get sockets set up for gdb stub	2020-07-24 08:46:00 -04:00
Dillon Beliveau	6265cda32c	handle pagemask correctly	2020-07-23 21:44:16 -04:00
Dillon Beliveau	a6a9115a31	Merge branch 'master' into tlb-wip	2020-07-23 01:08:17 -04:00
Dillon Beliveau	3b05af35d2	Cleanup print statements	2020-07-23 01:07:28 -04:00
Dillon Beliveau	6ac1fdee01	DDIV / DADDIU	2020-07-23 01:07:11 -04:00
Dillon Beliveau	b3d709c464	remove check	2020-07-23 00:45:04 -04:00
Dillon Beliveau	4a2b259645	sync RSP to CPU at correct ratio	2020-07-23 00:44:57 -04:00
Dillon Beliveau	4bae06422a	Rework DMA	2020-07-23 00:43:56 -04:00
Dillon Beliveau	a289063b97	fix LDV	2020-07-23 00:33:17 -04:00
Dillon Beliveau	68ec7e0525	Fix MTC2	2020-07-23 00:30:48 -04:00
Dillon Beliveau	c2fc742975	MFC2	2020-07-23 00:29:31 -04:00
Dillon Beliveau	d090bef4d8	LRV	2020-07-23 00:29:04 -04:00
Dillon Beliveau	3e5545b1e9	RSP SRLV	2020-07-23 00:17:15 -04:00
Dillon Beliveau	4cd1a78c89	fix offsets	2020-07-23 00:15:02 -04:00
Dillon Beliveau	0451fd418b	crash when RSP PC misaligned	2020-07-21 22:18:59 -04:00
Dillon Beliveau	3d6379b258	fix VMUDH	2020-07-20 19:02:22 -04:00
Dillon Beliveau	65c56cec4a	pass VMADM	2020-07-20 18:54:29 -04:00
Dillon Beliveau	40098f5d0f	use correct settings	2020-07-20 18:44:16 -04:00
Dillon Beliveau	a0f98083f1	fix log line	2020-07-19 17:49:57 -04:00
Dillon Beliveau	e1fcd6e9a1	fix VRCPH	2020-07-19 17:49:05 -04:00
Dillon Beliveau	a25106e31d	fix VADD	2020-07-19 17:48:53 -04:00
Dillon Beliveau	f20cd11f3a	fix VRCPL	2020-07-19 16:45:44 -04:00
Dillon Beliveau	d00a2d8e63	fix VLT	2020-07-19 16:07:48 -04:00
Dillon Beliveau	5cb8642580	VXOR/VNXOR set the acc as well	2020-07-19 16:00:27 -04:00
Dillon Beliveau	6ec013a332	rewrite VCH	2020-07-19 15:53:29 -04:00
Dillon Beliveau	c471fc0568	dumb typo	2020-07-19 15:40:26 -04:00
Dillon Beliveau	1976f74588	remove pseudocode comments	2020-07-19 14:20:59 -04:00
Dillon Beliveau	0f7ab14192	free(system)	2020-07-19 14:19:10 -04:00
Dillon Beliveau	cbf8bdf7b4	Fixing VCL	2020-07-19 14:19:02 -04:00
Dillon Beliveau	4df35426a7	endianness strikes again	2020-07-19 14:17:57 -04:00
Dillon Beliveau	103d15811a	VOR and VNOR set the accumulator too	2020-07-19 13:33:51 -04:00
Dillon Beliveau	36a3a3c380	VAND and VNAND set the accumulator too	2020-07-19 13:33:51 -04:00
Dillon Beliveau	a7fe26cc38	couple more (probably broken) RSP instructions	2020-07-19 13:02:07 -04:00
Dillon Beliveau	647b541a1f	VRCPH	2020-07-19 10:49:04 -04:00
Dillon Beliveau	80434c5fde	VMUDL	2020-07-18 20:18:41 -04:00
Dillon Beliveau	9911d9637b	VCL	2020-07-18 20:11:27 -04:00
Dillon Beliveau	4c493edc34	VCH	2020-07-18 20:11:19 -04:00
Dillon Beliveau	b1adb985e0	VADD	2020-07-18 20:11:05 -04:00
Dillon Beliveau	fda27a3459	fix RSP registers	2020-07-18 20:10:55 -04:00
Dillon Beliveau	4ab59dcb71	this passes now	2020-07-17 23:11:01 -04:00
Dillon Beliveau	ac772772a6	Don't clear RSP state in between subtest runs	2020-07-17 23:07:20 -04:00