mirror of
https://github.com/mupen64plus/mupen64plus-rsp-cxd4.git
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8857d37876
Although functionally there is no difference (when just looping vector elements from 0 to 7) between using a signed int or an unsigned int, repeatedly seeing an inconsistent mix in usage between the two across different vector functions has been an ongoing distraction for years. It should be the same everywhere, and between signed int and unsigned int, unsigned int is the type which always fits within size_t from stddef.h, the safe type for memory pointers and dereference indices.
236 lines
7.1 KiB
C
236 lines
7.1 KiB
C
/******************************************************************************\
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* Project: MSP Emulation Layer for Vector Unit Computational Operations *
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* Authors: Iconoclast *
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* Release: 2018.03.18 *
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* License: CC0 Public Domain Dedication *
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* *
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* To the extent possible under law, the author(s) have dedicated all copyright *
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* and related and neighboring rights to this software to the public domain *
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* worldwide. This software is distributed without any warranty. *
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* *
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* You should have received a copy of the CC0 Public Domain Dedication along *
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* with this software. *
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* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>. *
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\******************************************************************************/
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#include "vu.h"
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#include "multiply.h"
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#include "add.h"
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#include "select.h"
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#include "logical.h"
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#include "divide.h"
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#if 0
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#include "pack.h"
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#endif
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ALIGNED i16 VR[32][N << VR_STATIC_WRAPAROUND];
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ALIGNED i16 VACC[3][N];
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#ifndef ARCH_MIN_SSE2
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ALIGNED i16 V_result[N];
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#endif
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/*
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* These normally should have type `int` because they are Boolean T/F arrays.
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* However, since SSE2 uses 128-bit XMM's, and Win32 `int` storage is 32-bit,
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* we have the problem of 32*8 > 128 bits, so we use `short` to reduce packs.
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*/
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ALIGNED i16 cf_ne[N]; /* $vco: high "NOTEQUAL" */
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ALIGNED i16 cf_co[N]; /* $vco: low "carry/borrow in/out" */
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ALIGNED i16 cf_clip[N]; /* $vcc: high (clip tests: VCL, VCH, VCR) */
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ALIGNED i16 cf_comp[N]; /* $vcc: low (VEQ, VNE, VLT, VGE, VCL, VCH, VCR) */
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ALIGNED i16 cf_vce[N]; /* $vce: vector compare extension register */
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VECTOR_OPERATION res_V(v16 vs, v16 vt)
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{
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vt = vs; /* unused */
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message("C2\nRESERVED"); /* uncertain how to handle reserved, untested */
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#ifdef ARCH_MIN_SSE2
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vs = _mm_setzero_si128();
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return (vt = vs); /* -Wunused-but-set-parameter */
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#else
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vector_wipe(V_result);
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if (vt == vs)
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return; /* -Wunused-but-set-parameter */
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return;
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#endif
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}
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VECTOR_OPERATION res_M(v16 vs, v16 vt)
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{ /* Ultra64 OS did have these, so one could implement this ext. */
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message("VMUL IQ");
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#ifdef ARCH_MIN_SSE2
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vs = res_V(vs, vt);
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return (vs);
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#else
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res_V(vs, vt);
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return;
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#endif
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}
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/*
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* Op-code-accurate matrix of all the known RSP vector operations.
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* To do: Either remove VMACQ, or add VRNDP, VRNDN, and VMULQ.
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*
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* Note that these are not our literal function names, just macro names.
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*/
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VECTOR_OPERATION (*COP2_C2[8 * 8])(v16, v16) = {
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VMULF ,VMULU ,res_M ,res_M ,VMUDL ,VMUDM ,VMUDN ,VMUDH , /* 000 */
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VMACF ,VMACU ,res_M ,res_M ,VMADL ,VMADM ,VMADN ,VMADH , /* 001 */
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VADD ,VSUB ,res_V ,VABS ,VADDC ,VSUBC ,res_V ,res_V , /* 010 */
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res_V ,res_V ,res_V ,res_V ,res_V ,VSAW ,res_V ,res_V , /* 011 */
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VLT ,VEQ ,VNE ,VGE ,VCL ,VCH ,VCR ,VMRG , /* 100 */
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VAND ,VNAND ,VOR ,VNOR ,VXOR ,VNXOR ,res_V ,res_V , /* 101 */
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VRCP ,VRCPL ,VRCPH ,VMOV ,VRSQ ,VRSQL ,VRSQH ,VNOP , /* 110 */
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res_V ,res_V ,res_V ,res_V ,res_V ,res_V ,res_V ,res_V , /* 111 */
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}; /* 000 001 010 011 100 101 110 111 */
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#ifndef ARCH_MIN_SSE2
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u16 get_VCO(void)
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{
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register u16 vco;
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vco = 0x0000
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| (cf_ne[0xF % 8] << 0xF)
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| (cf_ne[0xE % 8] << 0xE)
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| (cf_ne[0xD % 8] << 0xD)
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| (cf_ne[0xC % 8] << 0xC)
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| (cf_ne[0xB % 8] << 0xB)
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| (cf_ne[0xA % 8] << 0xA)
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| (cf_ne[0x9 % 8] << 0x9)
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| (cf_ne[0x8 % 8] << 0x8)
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| (cf_co[0x7 % 8] << 0x7)
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| (cf_co[0x6 % 8] << 0x6)
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| (cf_co[0x5 % 8] << 0x5)
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| (cf_co[0x4 % 8] << 0x4)
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| (cf_co[0x3 % 8] << 0x3)
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| (cf_co[0x2 % 8] << 0x2)
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| (cf_co[0x1 % 8] << 0x1)
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| (cf_co[0x0 % 8] << 0x0);
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return (vco); /* Big endian becomes little. */
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}
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u16 get_VCC(void)
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{
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register u16 vcc;
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vcc = 0x0000
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| (cf_clip[0xF % 8] << 0xF)
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| (cf_clip[0xE % 8] << 0xE)
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| (cf_clip[0xD % 8] << 0xD)
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| (cf_clip[0xC % 8] << 0xC)
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| (cf_clip[0xB % 8] << 0xB)
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| (cf_clip[0xA % 8] << 0xA)
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| (cf_clip[0x9 % 8] << 0x9)
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| (cf_clip[0x8 % 8] << 0x8)
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| (cf_comp[0x7 % 8] << 0x7)
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| (cf_comp[0x6 % 8] << 0x6)
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| (cf_comp[0x5 % 8] << 0x5)
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| (cf_comp[0x4 % 8] << 0x4)
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| (cf_comp[0x3 % 8] << 0x3)
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| (cf_comp[0x2 % 8] << 0x2)
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| (cf_comp[0x1 % 8] << 0x1)
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| (cf_comp[0x0 % 8] << 0x0);
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return (vcc); /* Big endian becomes little. */
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}
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u8 get_VCE(void)
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{
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unsigned int result;
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register u8 vce;
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result = 0x00
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| (cf_vce[0x7] << 0x7)
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| (cf_vce[0x6] << 0x6)
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| (cf_vce[0x5] << 0x5)
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| (cf_vce[0x4] << 0x4)
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| (cf_vce[0x3] << 0x3)
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| (cf_vce[0x2] << 0x2)
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| (cf_vce[0x1] << 0x1)
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| (cf_vce[0x0] << 0x0)
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;
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vce = (u8)(result & 0xFF);
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return (vce); /* Big endian becomes little. */
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}
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#else
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u16 get_VCO(void)
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{
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v16 xmm, hi, lo;
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register u16 vco;
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hi = _mm_load_si128((v16 *)cf_ne);
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lo = _mm_load_si128((v16 *)cf_co);
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/*
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* Rotate Boolean storage from LSB to MSB.
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*/
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hi = _mm_slli_epi16(hi, 15);
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lo = _mm_slli_epi16(lo, 15);
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xmm = _mm_packs_epi16(lo, hi); /* Decompress INT16 Booleans to INT8 ones. */
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vco = _mm_movemask_epi8(xmm) & 0x0000FFFF; /* PMOVMSKB combines each MSB. */
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return (vco);
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}
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u16 get_VCC(void)
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{
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v16 xmm, hi, lo;
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register u16 vcc;
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hi = _mm_load_si128((v16 *)cf_clip);
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lo = _mm_load_si128((v16 *)cf_comp);
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/*
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* Rotate Boolean storage from LSB to MSB.
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*/
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hi = _mm_slli_epi16(hi, 15);
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lo = _mm_slli_epi16(lo, 15);
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xmm = _mm_packs_epi16(lo, hi); /* Decompress INT16 Booleans to INT8 ones. */
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vcc = _mm_movemask_epi8(xmm) & 0x0000FFFF; /* PMOVMSKB combines each MSB. */
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return (vcc);
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}
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u8 get_VCE(void)
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{
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v16 xmm, hi, lo;
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register u8 vce;
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hi = _mm_setzero_si128();
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lo = _mm_load_si128((v16 *)cf_vce);
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lo = _mm_slli_epi16(lo, 15); /* Rotate Boolean storage from LSB to MSB. */
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xmm = _mm_packs_epi16(lo, hi); /* Decompress INT16 Booleans to INT8 ones. */
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vce = _mm_movemask_epi8(xmm) & 0x000000FF; /* PMOVMSKB combines each MSB. */
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return (vce);
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}
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#endif
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/*
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* CTC2 resources
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* not sure how to vectorize going the other direction into SSE2
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*/
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void set_VCO(u16 vco)
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{
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register unsigned int i;
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for (i = 0; i < N; i++)
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cf_co[i] = (vco >> (i + 0x0)) & 1;
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for (i = 0; i < N; i++)
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cf_ne[i] = (vco >> (i + 0x8)) & 1;
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return; /* Little endian becomes big. */
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}
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void set_VCC(u16 vcc)
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{
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register unsigned int i;
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for (i = 0; i < N; i++)
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cf_comp[i] = (vcc >> (i + 0x0)) & 1;
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for (i = 0; i < N; i++)
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cf_clip[i] = (vcc >> (i + 0x8)) & 1;
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return; /* Little endian becomes big. */
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}
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void set_VCE(u8 vce)
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{
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register unsigned int i;
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for (i = 0; i < N; i++)
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cf_vce[i] = (vce >> i) & 1;
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return; /* Little endian becomes big. */
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}
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