unknown
cbf49ef41c
rewrote J and JAL
2015-11-28 20:11:14 -05:00
unknown
4ccd6e8ee4
a few more trivial clean-ups
2015-11-28 19:51:05 -05:00
unknown
5acda69b15
rewrote BEQ, BNE, BLEZ and BGTZ
2015-11-28 18:58:29 -05:00
unknown
bdf9e27020
rewrote ADDI[U], SLTI and SLTIU
2015-11-28 16:21:10 -05:00
unknown
f790f4975e
For bit-wise portability, GPR file should not be signed.
2015-11-28 16:07:32 -05:00
unknown
3760de8c96
rewrote ANDI, ORI, XORI and LUI
2015-11-28 15:30:39 -05:00
unknown
abf4981928
Enumerate the list of GPR assembler syntax names.
2015-11-28 14:55:44 -05:00
unknown
f9579c1d47
rewrote LB, LBU, LH, LHU, LW, SB, SH and SW
2015-11-28 14:15:12 -05:00
unknown
0cb4e5a6e4
#define PROFILE_MODE to prefer speed vs. benchmark precision
2015-11-28 12:41:21 -05:00
unknown
43ef2e2292
split R4000 CPU interpreter cycle to its own function
2015-11-28 10:27:46 -05:00
unknown
aad3ecf3f8
CONTINUE macro #define should be deleted.
...
#ifdef EMULATE_STATIC_PC, then `break;' should compile effectively into a `continue;' during optimizations. I need this change for flexibility in restructuring the instruction decode functions later.
2015-11-28 10:18:20 -05:00
unknown
776e50df85
EMULATE_STATIC_PC #define moved to header
2015-11-28 00:40:10 -05:00
unknown
d807c78226
some trivial clean-ups
2015-11-27 19:40:39 -05:00
Gillou68310
aaed3b5b35
Fixed undefined reference to _m_empty when building on x64
...
MMX is not used so this is not necessary anyway
2015-11-10 13:38:22 +01:00
Gillou68310
8796295a2c
Merge commit '73232513e7889c82f86fd77f81ac6a060fe7d828'
2015-11-10 11:57:18 +01:00
unknown
cd7c41482a
For better PIC linkage, remove SHUFFLE_VECTOR.
...
Also got rid of the SSE2 code for shuffling. It takes too much extra byte code in the main interpreter instruction cache and requires an extra branch anyway, and an SSSE3 solution would still require at least 3 such large SIMD instructions anyway. So let's see if we can't safely overhaul this without a speed drop.
2015-08-17 11:09:01 -04:00
unknown
690bb76c47
Do the same commit as before, but with rt'/vt'.
2015-06-08 00:30:43 -04:00
unknown
526d26286e
Do the same commit as before, but for rs'/vs' this time.
2015-06-08 00:14:28 -04:00
unknown
fcde75afdc
Optimize register allocation and timing: Do not set rd globally.
...
My old reasoning behind that method was that the compiler would decide where to inline setting rd within which switch cases on my own, but now I can see it best plainly to decide for myself where rd should be locally initialized. This also helps prevent the problem of assigning a bitmask to the rd register specifier as an unnecessary precaution for op-codes that don't even access register[rd].
2015-06-07 23:22:29 -04:00
unknown
e1adbad4c1
made MFC0 timeout dynamic--starts out high and slow, ends up fast
2015-03-10 20:32:21 -04:00
Conchúr Navid
483a65bd6b
Add comment that +AL opcodes are expected to fall through switch
...
This should help static code analyzers to detect this a intentionally.
2015-03-05 10:38:48 +01:00
unknown
8f3bb68fc3
supporting unaligned data memory addresses in Battle for Naboo
2015-02-24 22:43:29 -05:00
unknown
c40a4eff31
optimized LWC2 and SWC2 offset decoding
2015-02-18 22:01:19 -05:00
unknown
c7c7f9c54d
fixed CPU resume regression from within RSP
2015-02-18 21:44:20 -05:00
unknown
bf78043f7c
handling DMA read when address exceeds boundary (BattleTanx)
2015-02-18 21:04:19 -05:00
unknown
58c9e9f135
uh
2015-02-18 19:04:53 -05:00
unknown
b4d5e29c4e
duplicated comment...already existed in su.h at correct location
2015-02-18 19:01:46 -05:00
unknown
452456eed1
Avoid nesting comments.
2015-02-18 18:50:54 -05:00
unknown
09520e8381
Only correct CPU-RSP semaphore if no HLE code involving plugin types.
2015-02-18 16:30:17 -05:00
unknown
c4e06883ad
now permanently enabling infinite loop detection
...
Since the MF SP status timeout is so high (currently 8192), no games ever seem to reach such a high count, so making this a configurable option whether to break out of infinite RSP loops seems kind of pointless. The case would only arise once a game actually required the option anyway.
2015-02-18 15:32:05 -05:00
unknown
96e01f13c4
think I meant to keep the macro in the .h, not the .c
2015-02-18 15:06:36 -05:00
unknown
6309a52073
fixed LTV regression from moving to unsigned types
2015-02-06 16:53:35 -05:00
no
9e0328f45b
Fix GNU assembler syntax errors by prefixing vcr's with cf_.
2015-01-30 14:16:55 -05:00
unknown
23d9eb1b6a
missed some lines in previous commit
2015-01-29 11:31:27 -05:00
unknown
c90be1f99c
enforcing unsigned types for bit masks and bit-sensitive work
2015-01-29 08:58:37 -05:00
unknown
8c6bbc1c1e
freed some cache space by not encompassing rd overflow in LUT
2015-01-28 16:46:09 -05:00
unknown
7eeed8190f
changed MFC0 timeout interval from 8 to 8192 (stable, helps test)
2015-01-27 21:20:30 -05:00
unknown
7d1350b248
more enforcement of zero-extension with higher-precision literals
2015-01-27 20:49:46 -05:00
unknown
95cf462dfb
force dummy buffer allocations for LWC2, native SWC2 wraparound
2015-01-21 15:10:18 -05:00
unknown
596fccbfb1
should loop addr in Boss Game ucodes with illegal SDV
2015-01-18 17:54:50 -05:00
no
e5e80738bd
fix Linux port segfault from Mupen64 0.5 name collision
2014-12-25 18:26:57 -05:00
unknown
b315f14bf5
interpreter CPU loop condition now reads just an int, not int & 1
2014-12-13 17:26:55 -05:00
unknown
9c49dc4fff
abolish SSSE3 configurator for byte-wise shuffling
2014-12-13 16:34:48 -05:00
unknown
dd32120278
re-install function pointer tables for LWC2 and SWC2
2014-12-11 06:34:01 -05:00
unknown
5fa24d02a2
update outdated code when EMULATE_STATIC_PC not defined
2014-12-11 05:19:17 -05:00
unknown
0fe1edd89a
optional feature to execute EMMS in case MMX code was generated
2014-12-11 04:38:42 -05:00
unknown
eb6171c6eb
forgot a couple more pointer type installations in SP DMA
2014-12-11 04:29:33 -05:00
unknown
699896f677
install new pointer types to distinguish mem. reference from decl.'s
2014-12-08 23:47:50 -05:00
unknown
2e1e9edf75
cut SHUFFLE_VECTOR to only 2 arguments with pre-loaded VT
2014-10-17 02:23:08 -04:00
unknown
158a4d0b60
pass only 2 XMM operands, w/ no return slot ifndef ARCH_MIN_SSE2
2014-10-16 00:43:37 -04:00
