mirror of
https://github.com/mupen64plus/mupen64plus-oldsvn.git
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154 lines
4.8 KiB
C
154 lines
4.8 KiB
C
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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* Mupen64plus - gcop1.c *
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* Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
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* Copyright (C) 2007 Richard Goedeken (Richard42) *
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* Copyright (C) 2002 Hacktarux *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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#include <stdio.h>
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#include "assemble.h"
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#include "interpret.h"
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#include "../recomph.h"
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#include "../recomp.h"
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#include "../r4300.h"
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#include "../ops.h"
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#include "../macros.h"
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#include "../../memory/memory.h"
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void genmfc1(void)
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{
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#if defined(COUNT_INSTR)
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inc_m32abs(&instr_count[111]);
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#endif
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#ifdef INTERPRET_MFC1
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gencallinterp((unsigned long long)MFC1, 0);
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#else
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gencheck_cop1_unusable();
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mov_reg64_m64abs(RAX, (unsigned long long *)(®_cop1_simple[dst->f.r.nrd]));
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mov_reg32_preg64(EBX, RAX);
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mov_m32abs_reg32((unsigned int*)dst->f.r.rt, EBX);
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sar_reg32_imm8(EBX, 31);
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mov_m32abs_reg32(((unsigned int*)dst->f.r.rt)+1, EBX);
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#endif
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}
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void gendmfc1(void)
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{
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#if defined(COUNT_INSTR)
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inc_m32abs(&instr_count[112]);
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#endif
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#ifdef INTERPRET_DMFC1
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gencallinterp((unsigned long long)DMFC1, 0);
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#else
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gencheck_cop1_unusable();
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mov_reg64_m64abs(RAX, (unsigned long long *) (®_cop1_double[dst->f.r.nrd]));
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mov_reg32_preg64(EBX, RAX);
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mov_reg32_preg64pimm32(ECX, RAX, 4);
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mov_m32abs_reg32((unsigned int*)dst->f.r.rt, EBX);
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mov_m32abs_reg32(((unsigned int*)dst->f.r.rt)+1, ECX);
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#endif
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}
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void gencfc1(void)
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{
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#if defined(COUNT_INSTR)
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inc_m32abs(&instr_count[113]);
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#endif
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#ifdef INTERPRET_CFC1
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gencallinterp((unsigned long long)CFC1, 0);
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#else
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gencheck_cop1_unusable();
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if(dst->f.r.nrd == 31) mov_reg32_m32abs(EAX, (unsigned int*)&FCR31);
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else mov_reg32_m32abs(EAX, (unsigned int*)&FCR0);
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mov_m32abs_reg32((unsigned int*)dst->f.r.rt, EAX);
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sar_reg32_imm8(EAX, 31);
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mov_m32abs_reg32(((unsigned int*)dst->f.r.rt)+1, EAX);
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#endif
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}
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void genmtc1(void)
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{
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#if defined(COUNT_INSTR)
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inc_m32abs(&instr_count[114]);
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#endif
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#ifdef INTERPRET_MTC1
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gencallinterp((unsigned long long)MTC1, 0);
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#else
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gencheck_cop1_unusable();
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mov_reg32_m32abs(EAX, (unsigned int*)dst->f.r.rt);
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mov_reg64_m64abs(RBX, (unsigned long long *)(®_cop1_simple[dst->f.r.nrd]));
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mov_preg64_reg32(RBX, EAX);
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#endif
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}
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void gendmtc1(void)
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{
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#if defined(COUNT_INSTR)
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inc_m32abs(&instr_count[115]);
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#endif
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#ifdef INTERPRET_DMTC1
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gencallinterp((unsigned long long)DMTC1, 0);
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#else
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gencheck_cop1_unusable();
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mov_reg32_m32abs(EAX, (unsigned int*)dst->f.r.rt);
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mov_reg32_m32abs(EBX, ((unsigned int*)dst->f.r.rt)+1);
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mov_reg64_m64abs(RDX, (unsigned long long *)(®_cop1_double[dst->f.r.nrd]));
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mov_preg64_reg32(RDX, EAX);
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mov_preg64pimm32_reg32(RDX, 4, EBX);
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#endif
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}
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void genctc1(void)
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{
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#if defined(COUNT_INSTR)
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inc_m32abs(&instr_count[116]);
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#endif
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#ifdef INTERPRET_CTC1
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gencallinterp((unsigned long long)CTC1, 0);
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#else
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gencheck_cop1_unusable();
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if (dst->f.r.nrd != 31) return;
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mov_reg32_m32abs(EAX, (unsigned int*)dst->f.r.rt);
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mov_m32abs_reg32((unsigned int*)&FCR31, EAX);
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and_eax_imm32(3);
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cmp_eax_imm32(0);
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jne_rj(13);
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mov_m32abs_imm32((unsigned int*)&rounding_mode, 0x33F); // 11
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jmp_imm_short(51); // 2
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cmp_eax_imm32(1); // 5
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jne_rj(13); // 2
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mov_m32abs_imm32((unsigned int*)&rounding_mode, 0xF3F); // 11
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jmp_imm_short(31); // 2
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cmp_eax_imm32(2); // 5
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jne_rj(13); // 2
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mov_m32abs_imm32((unsigned int*)&rounding_mode, 0xB3F); // 11
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jmp_imm_short(11); // 2
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mov_m32abs_imm32((unsigned int*)&rounding_mode, 0x73F); // 11
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fldcw_m16abs((unsigned short*)&rounding_mode);
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#endif
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}
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