mirror of
https://github.com/mupen64plus/mupen64plus-oldsvn.git
synced 2025-04-02 10:52:35 -04:00
869 lines
22 KiB
C
869 lines
22 KiB
C
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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* Mupen64plus - regcache.c *
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* Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
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* Copyright (C) 2002 Hacktarux *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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#include <stdio.h>
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#include "regcache.h"
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#include "../recomp.h"
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#include "../r4300.h"
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#include "../recomph.h"
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static unsigned int* reg_content[8];
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static precomp_instr* last_access[8];
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static precomp_instr* free_since[8];
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static int dirty[8];
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static int r64[8];
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static unsigned int* r0;
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void init_cache(precomp_instr* start)
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{
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int i;
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for (i=0; i<8; i++)
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{
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last_access[i] = NULL;
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free_since[i] = start;
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}
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r0 = (unsigned int*)reg;
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}
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void free_all_registers(void)
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{
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#if defined(PROFILE_R4300)
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int freestart = code_length;
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int flushed = 0;
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#endif
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int i;
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for (i=0; i<8; i++)
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{
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#if defined(PROFILE_R4300)
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if (last_access[i] && dirty[i]) flushed = 1;
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#endif
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if (last_access[i]) free_register(i);
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else
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{
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while (free_since[i] <= dst)
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{
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free_since[i]->reg_cache_infos.needed_registers[i] = NULL;
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free_since[i]++;
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}
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}
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}
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#if defined(PROFILE_R4300)
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if (flushed == 1)
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{
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long x86addr = (long) ((*inst_pointer) + freestart);
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int mipsop = -5;
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fwrite(&mipsop, 1, 4, pfProfile); /* -5 = regcache flushing */
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fwrite(&x86addr, 1, sizeof(char *), pfProfile); // write pointer to start of register cache flushing instructions
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x86addr = (long) ((*inst_pointer) + code_length);
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fwrite(&src, 1, 4, pfProfile); // write 4-byte MIPS opcode for current instruction
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fwrite(&x86addr, 1, sizeof(char *), pfProfile); // write pointer to dynamically generated x86 code for this MIPS instruction
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}
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#endif
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}
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// this function frees a specific X86 GPR
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void free_register(int reg)
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{
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precomp_instr *last;
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if (last_access[reg] != NULL &&
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r64[reg] != -1 && (int)reg_content[reg] != (int)reg_content[r64[reg]]-4)
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{
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free_register(r64[reg]);
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return;
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}
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if (last_access[reg] != NULL) last = last_access[reg]+1;
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else last = free_since[reg];
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while (last <= dst)
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{
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if (last_access[reg] != NULL && dirty[reg])
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last->reg_cache_infos.needed_registers[reg] = reg_content[reg];
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else
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last->reg_cache_infos.needed_registers[reg] = NULL;
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if (last_access[reg] != NULL && r64[reg] != -1)
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{
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if (dirty[r64[reg]])
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last->reg_cache_infos.needed_registers[r64[reg]] = reg_content[r64[reg]];
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else
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last->reg_cache_infos.needed_registers[r64[reg]] = NULL;
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}
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last++;
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}
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if (last_access[reg] == NULL)
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{
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free_since[reg] = dst+1;
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return;
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}
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if (dirty[reg])
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{
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mov_m32_reg32(reg_content[reg], reg);
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if (r64[reg] == -1)
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{
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sar_reg32_imm8(reg, 31);
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mov_m32_reg32((unsigned int*)reg_content[reg]+1, reg);
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}
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else mov_m32_reg32(reg_content[r64[reg]], r64[reg]);
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}
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last_access[reg] = NULL;
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free_since[reg] = dst+1;
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if (r64[reg] != -1)
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{
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last_access[r64[reg]] = NULL;
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free_since[r64[reg]] = dst+1;
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}
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}
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int lru_register(void)
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{
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unsigned int oldest_access = 0xFFFFFFFF;
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int i, reg = 0;
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for (i=0; i<8; i++)
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{
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if (i != ESP && (unsigned int)last_access[i] < oldest_access)
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{
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oldest_access = (int)last_access[i];
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reg = i;
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}
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}
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return reg;
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}
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int lru_register_exc1(int exc1)
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{
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unsigned int oldest_access = 0xFFFFFFFF;
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int i, reg = 0;
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for (i=0; i<8; i++)
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{
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if (i != ESP && i != exc1 && (unsigned int)last_access[i] < oldest_access)
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{
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oldest_access = (int)last_access[i];
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reg = i;
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}
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}
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return reg;
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}
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// this function finds a register to put the data contained in addr,
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// if there was another value before it's cleanly removed of the
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// register cache. After that, the register number is returned.
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// If data are already cached, the function only returns the register number
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int allocate_register(unsigned int *addr)
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{
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unsigned int oldest_access = 0xFFFFFFFF;
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int reg = 0, i;
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// is it already cached ?
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if (addr != NULL)
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{
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for (i=0; i<8; i++)
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{
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if (last_access[i] != NULL && reg_content[i] == addr)
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{
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precomp_instr *last = last_access[i]+1;
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while (last <= dst)
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{
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last->reg_cache_infos.needed_registers[i] = reg_content[i];
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last++;
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}
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last_access[i] = dst;
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if (r64[i] != -1)
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{
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last = last_access[r64[i]]+1;
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while (last <= dst)
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{
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last->reg_cache_infos.needed_registers[r64[i]] = reg_content[r64[i]];
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last++;
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}
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last_access[r64[i]] = dst;
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}
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return i;
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}
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}
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}
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// if it's not cached, we take the least recently used register
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for (i=0; i<8; i++)
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{
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if (i != ESP && (unsigned int)last_access[i] < oldest_access)
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{
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oldest_access = (int)last_access[i];
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reg = i;
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}
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}
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if (last_access[reg]) free_register(reg);
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else
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{
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while (free_since[reg] <= dst)
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{
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free_since[reg]->reg_cache_infos.needed_registers[reg] = NULL;
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free_since[reg]++;
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}
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}
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last_access[reg] = dst;
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reg_content[reg] = addr;
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dirty[reg] = 0;
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r64[reg] = -1;
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if (addr != NULL)
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{
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if (addr == r0 || addr == r0+1)
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xor_reg32_reg32(reg, reg);
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else
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mov_reg32_m32(reg, addr);
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}
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return reg;
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}
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// this function is similar to allocate_register except it loads
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// a 64 bits value, and return the register number of the LSB part
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int allocate_64_register1(unsigned int *addr)
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{
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int reg1, reg2, i;
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// is it already cached as a 32 bits value ?
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for (i=0; i<8; i++)
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{
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if (last_access[i] != NULL && reg_content[i] == addr)
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{
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if (r64[i] == -1)
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{
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allocate_register(addr);
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reg2 = allocate_register(dirty[i] ? NULL : addr+1);
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r64[i] = reg2;
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r64[reg2] = i;
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if (dirty[i])
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{
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reg_content[reg2] = addr+1;
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dirty[reg2] = 1;
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mov_reg32_reg32(reg2, i);
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sar_reg32_imm8(reg2, 31);
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}
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return i;
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}
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}
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}
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reg1 = allocate_register(addr);
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reg2 = allocate_register(addr+1);
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r64[reg1] = reg2;
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r64[reg2] = reg1;
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return reg1;
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}
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// this function is similar to allocate_register except it loads
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// a 64 bits value, and return the register number of the MSB part
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int allocate_64_register2(unsigned int *addr)
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{
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int reg1, reg2, i;
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// is it already cached as a 32 bits value ?
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for (i=0; i<8; i++)
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{
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if (last_access[i] != NULL && reg_content[i] == addr)
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{
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if (r64[i] == -1)
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{
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allocate_register(addr);
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reg2 = allocate_register(dirty[i] ? NULL : addr+1);
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r64[i] = reg2;
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r64[reg2] = i;
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if (dirty[i])
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{
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reg_content[reg2] = addr+1;
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dirty[reg2] = 1;
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mov_reg32_reg32(reg2, i);
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sar_reg32_imm8(reg2, 31);
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}
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return reg2;
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}
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}
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}
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reg1 = allocate_register(addr);
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reg2 = allocate_register(addr+1);
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r64[reg1] = reg2;
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r64[reg2] = reg1;
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return reg2;
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}
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// this function checks if the data located at addr are cached in a register
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// and then, it returns 1 if it's a 64 bit value
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// 0 if it's a 32 bit value
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// -1 if it's not cached
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int is64(unsigned int *addr)
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{
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int i;
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for (i=0; i<8; i++)
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{
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if (last_access[i] != NULL && reg_content[i] == addr)
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{
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if (r64[i] == -1) return 0;
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return 1;
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}
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}
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return -1;
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}
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int allocate_register_w(unsigned int *addr)
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{
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unsigned int oldest_access = 0xFFFFFFFF;
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int reg = 0, i;
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// is it already cached ?
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for (i=0; i<8; i++)
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{
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if (last_access[i] != NULL && reg_content[i] == addr)
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{
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precomp_instr *last = last_access[i]+1;
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while (last <= dst)
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{
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last->reg_cache_infos.needed_registers[i] = NULL;
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last++;
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}
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last_access[i] = dst;
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dirty[i] = 1;
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if (r64[i] != -1)
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{
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last = last_access[r64[i]]+1;
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while (last <= dst)
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{
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last->reg_cache_infos.needed_registers[r64[i]] = NULL;
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last++;
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}
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free_since[r64[i]] = dst+1;
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last_access[r64[i]] = NULL;
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r64[i] = -1;
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}
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return i;
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}
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}
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// if it's not cached, we take the least recently used register
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for (i=0; i<8; i++)
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{
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if (i != ESP && (unsigned int)last_access[i] < oldest_access)
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{
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oldest_access = (int)last_access[i];
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reg = i;
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}
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}
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if (last_access[reg]) free_register(reg);
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else
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{
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while (free_since[reg] <= dst)
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{
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free_since[reg]->reg_cache_infos.needed_registers[reg] = NULL;
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free_since[reg]++;
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}
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}
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last_access[reg] = dst;
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reg_content[reg] = addr;
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dirty[reg] = 1;
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r64[reg] = -1;
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return reg;
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}
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int allocate_64_register1_w(unsigned int *addr)
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{
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int reg1, reg2, i;
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// is it already cached as a 32 bits value ?
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for (i=0; i<8; i++)
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{
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if (last_access[i] != NULL && reg_content[i] == addr)
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{
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if (r64[i] == -1)
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{
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allocate_register_w(addr);
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reg2 = lru_register();
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if (last_access[reg2]) free_register(reg2);
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else
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{
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while (free_since[reg2] <= dst)
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{
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free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL;
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free_since[reg2]++;
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}
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}
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r64[i] = reg2;
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r64[reg2] = i;
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last_access[reg2] = dst;
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reg_content[reg2] = addr+1;
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dirty[reg2] = 1;
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mov_reg32_reg32(reg2, i);
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sar_reg32_imm8(reg2, 31);
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return i;
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}
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else
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{
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last_access[i] = dst;
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last_access[r64[i]] = dst;
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dirty[i] = dirty[r64[i]] = 1;
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return i;
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}
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}
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}
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reg1 = allocate_register_w(addr);
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reg2 = lru_register();
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if (last_access[reg2]) free_register(reg2);
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else
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{
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while (free_since[reg2] <= dst)
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{
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free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL;
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free_since[reg2]++;
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}
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}
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r64[reg1] = reg2;
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r64[reg2] = reg1;
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last_access[reg2] = dst;
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reg_content[reg2] = addr+1;
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dirty[reg2] = 1;
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return reg1;
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}
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int allocate_64_register2_w(unsigned int *addr)
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{
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int reg1, reg2, i;
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// is it already cached as a 32 bits value ?
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for (i=0; i<8; i++)
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{
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if (last_access[i] != NULL && reg_content[i] == addr)
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{
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if (r64[i] == -1)
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{
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allocate_register_w(addr);
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reg2 = lru_register();
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if (last_access[reg2]) free_register(reg2);
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else
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{
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while (free_since[reg2] <= dst)
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{
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free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL;
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free_since[reg2]++;
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}
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}
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r64[i] = reg2;
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r64[reg2] = i;
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last_access[reg2] = dst;
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reg_content[reg2] = addr+1;
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dirty[reg2] = 1;
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mov_reg32_reg32(reg2, i);
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sar_reg32_imm8(reg2, 31);
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return reg2;
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}
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else
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{
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last_access[i] = dst;
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last_access[r64[i]] = dst;
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dirty[i] = dirty[r64[i]] = 1;
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return r64[i];
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}
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}
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}
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reg1 = allocate_register_w(addr);
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reg2 = lru_register();
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if (last_access[reg2]) free_register(reg2);
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else
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{
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while (free_since[reg2] <= dst)
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{
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free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL;
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free_since[reg2]++;
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}
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}
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r64[reg1] = reg2;
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r64[reg2] = reg1;
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last_access[reg2] = dst;
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reg_content[reg2] = addr+1;
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dirty[reg2] = 1;
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return reg2;
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}
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void set_register_state(int reg, unsigned int *addr, int d)
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{
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last_access[reg] = dst;
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reg_content[reg] = addr;
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r64[reg] = -1;
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dirty[reg] = d;
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}
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void set_64_register_state(int reg1, int reg2, unsigned int *addr, int d)
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{
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last_access[reg1] = dst;
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last_access[reg2] = dst;
|
|
reg_content[reg1] = addr;
|
|
reg_content[reg2] = addr+1;
|
|
r64[reg1] = reg2;
|
|
r64[reg2] = reg1;
|
|
dirty[reg1] = d;
|
|
dirty[reg2] = d;
|
|
}
|
|
|
|
void lock_register(int reg)
|
|
{
|
|
free_register(reg);
|
|
last_access[reg] = (precomp_instr *)0xFFFFFFFF;
|
|
reg_content[reg] = NULL;
|
|
}
|
|
|
|
void unlock_register(int reg)
|
|
{
|
|
last_access[reg] = NULL;
|
|
}
|
|
|
|
void force_32(int reg)
|
|
{
|
|
if (r64[reg] != -1)
|
|
{
|
|
precomp_instr *last = last_access[reg]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
if (dirty[reg])
|
|
last->reg_cache_infos.needed_registers[reg] = reg_content[reg];
|
|
else
|
|
last->reg_cache_infos.needed_registers[reg] = NULL;
|
|
|
|
if (dirty[r64[reg]])
|
|
last->reg_cache_infos.needed_registers[r64[reg]] = reg_content[r64[reg]];
|
|
else
|
|
last->reg_cache_infos.needed_registers[r64[reg]] = NULL;
|
|
|
|
last++;
|
|
}
|
|
|
|
if (dirty[reg])
|
|
{
|
|
mov_m32_reg32(reg_content[reg], reg);
|
|
mov_m32_reg32(reg_content[r64[reg]], r64[reg]);
|
|
dirty[reg] = 0;
|
|
}
|
|
last_access[r64[reg]] = NULL;
|
|
free_since[r64[reg]] = dst+1;
|
|
r64[reg] = -1;
|
|
}
|
|
}
|
|
|
|
void allocate_register_manually(int reg, unsigned int *addr)
|
|
{
|
|
int i;
|
|
|
|
if (last_access[reg] != NULL && reg_content[reg] == addr)
|
|
{
|
|
precomp_instr *last = last_access[reg]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[reg] = reg_content[reg];
|
|
last++;
|
|
}
|
|
last_access[reg] = dst;
|
|
if (r64[reg] != -1)
|
|
{
|
|
last = last_access[r64[reg]]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[r64[reg]] = reg_content[r64[reg]];
|
|
last++;
|
|
}
|
|
last_access[r64[reg]] = dst;
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (last_access[reg]) free_register(reg);
|
|
else
|
|
{
|
|
while (free_since[reg] <= dst)
|
|
{
|
|
free_since[reg]->reg_cache_infos.needed_registers[reg] = NULL;
|
|
free_since[reg]++;
|
|
}
|
|
}
|
|
|
|
// is it already cached ?
|
|
for (i=0; i<8; i++)
|
|
{
|
|
if (last_access[i] != NULL && reg_content[i] == addr)
|
|
{
|
|
precomp_instr *last = last_access[i]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[i] = reg_content[i];
|
|
last++;
|
|
}
|
|
last_access[i] = dst;
|
|
if (r64[i] != -1)
|
|
{
|
|
last = last_access[r64[i]]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[r64[i]] = reg_content[r64[i]];
|
|
last++;
|
|
}
|
|
last_access[r64[i]] = dst;
|
|
}
|
|
|
|
mov_reg32_reg32(reg, i);
|
|
last_access[reg] = dst;
|
|
r64[reg] = r64[i];
|
|
if (r64[reg] != -1) r64[r64[reg]] = reg;
|
|
dirty[reg] = dirty[i];
|
|
reg_content[reg] = reg_content[i];
|
|
free_since[i] = dst+1;
|
|
last_access[i] = NULL;
|
|
|
|
return;
|
|
}
|
|
}
|
|
|
|
last_access[reg] = dst;
|
|
reg_content[reg] = addr;
|
|
dirty[reg] = 0;
|
|
r64[reg] = -1;
|
|
|
|
if (addr != NULL)
|
|
{
|
|
if (addr == r0 || addr == r0+1)
|
|
xor_reg32_reg32(reg, reg);
|
|
else
|
|
mov_reg32_m32(reg, addr);
|
|
}
|
|
}
|
|
|
|
void allocate_register_manually_w(int reg, unsigned int *addr, int load)
|
|
{
|
|
int i;
|
|
|
|
if (last_access[reg] != NULL && reg_content[reg] == addr)
|
|
{
|
|
precomp_instr *last = last_access[reg]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[reg] = reg_content[reg];
|
|
last++;
|
|
}
|
|
last_access[reg] = dst;
|
|
|
|
if (r64[reg] != -1)
|
|
{
|
|
last = last_access[r64[reg]]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[r64[reg]] = reg_content[r64[reg]];
|
|
last++;
|
|
}
|
|
last_access[r64[reg]] = NULL;
|
|
free_since[r64[reg]] = dst+1;
|
|
r64[reg] = -1;
|
|
}
|
|
dirty[reg] = 1;
|
|
return;
|
|
}
|
|
|
|
if (last_access[reg]) free_register(reg);
|
|
else
|
|
{
|
|
while (free_since[reg] <= dst)
|
|
{
|
|
free_since[reg]->reg_cache_infos.needed_registers[reg] = NULL;
|
|
free_since[reg]++;
|
|
}
|
|
}
|
|
|
|
// is it already cached ?
|
|
for (i=0; i<8; i++)
|
|
{
|
|
if (last_access[i] != NULL && reg_content[i] == addr)
|
|
{
|
|
precomp_instr *last = last_access[i]+1;
|
|
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[i] = reg_content[i];
|
|
last++;
|
|
}
|
|
last_access[i] = dst;
|
|
if (r64[i] != -1)
|
|
{
|
|
last = last_access[r64[i]]+1;
|
|
while (last <= dst)
|
|
{
|
|
last->reg_cache_infos.needed_registers[r64[i]] = NULL;
|
|
last++;
|
|
}
|
|
free_since[r64[i]] = dst+1;
|
|
last_access[r64[i]] = NULL;
|
|
r64[i] = -1;
|
|
}
|
|
|
|
if (load)
|
|
mov_reg32_reg32(reg, i);
|
|
last_access[reg] = dst;
|
|
dirty[reg] = 1;
|
|
r64[reg] = -1;
|
|
reg_content[reg] = reg_content[i];
|
|
free_since[i] = dst+1;
|
|
last_access[i] = NULL;
|
|
|
|
return;
|
|
}
|
|
}
|
|
|
|
last_access[reg] = dst;
|
|
reg_content[reg] = addr;
|
|
dirty[reg] = 1;
|
|
r64[reg] = -1;
|
|
|
|
if (addr != NULL && load)
|
|
{
|
|
if (addr == r0 || addr == r0+1)
|
|
xor_reg32_reg32(reg, reg);
|
|
else
|
|
mov_reg32_m32(reg, addr);
|
|
}
|
|
}
|
|
|
|
// 0x81 0xEC 0x4 0x0 0x0 0x0 sub esp, 4
|
|
// 0xA1 0xXXXXXXXX mov eax, XXXXXXXX (&code start)
|
|
// 0x05 0xXXXXXXXX add eax, XXXXXXXX (local_addr)
|
|
// 0x89 0x04 0x24 mov [esp], eax
|
|
// 0x8B (reg<<3)|5 0xXXXXXXXX mov eax, [XXXXXXXX]
|
|
// 0x8B (reg<<3)|5 0xXXXXXXXX mov ebx, [XXXXXXXX]
|
|
// 0x8B (reg<<3)|5 0xXXXXXXXX mov ecx, [XXXXXXXX]
|
|
// 0x8B (reg<<3)|5 0xXXXXXXXX mov edx, [XXXXXXXX]
|
|
// 0x8B (reg<<3)|5 0xXXXXXXXX mov ebp, [XXXXXXXX]
|
|
// 0x8B (reg<<3)|5 0xXXXXXXXX mov esi, [XXXXXXXX]
|
|
// 0x8B (reg<<3)|5 0xXXXXXXXX mov edi, [XXXXXXXX]
|
|
// 0xC3 ret
|
|
// total : 62 bytes
|
|
void build_wrapper(precomp_instr *instr, unsigned char* code, precomp_block* block)
|
|
{
|
|
int i;
|
|
int j=0;
|
|
|
|
#if defined(PROFILE_R4300)
|
|
long x86addr = (long) code;
|
|
int mipsop = -4;
|
|
fwrite(&mipsop, 1, 4, pfProfile); // write 4-byte MIPS opcode
|
|
fwrite(&x86addr, 1, sizeof(char *), pfProfile); // write pointer to dynamically generated x86 code for this MIPS instruction
|
|
#endif
|
|
|
|
code[j++] = 0x81;
|
|
code[j++] = 0xEC;
|
|
code[j++] = 0x04;
|
|
code[j++] = 0x00;
|
|
code[j++] = 0x00;
|
|
code[j++] = 0x00;
|
|
|
|
code[j++] = 0xA1;
|
|
*((unsigned int*)&code[j]) = (unsigned int)(&block->code);
|
|
j+=4;
|
|
|
|
code[j++] = 0x05;
|
|
*((unsigned int*)&code[j]) = (unsigned int)instr->local_addr;
|
|
j+=4;
|
|
|
|
code[j++] = 0x89;
|
|
code[j++] = 0x04;
|
|
code[j++] = 0x24;
|
|
|
|
for (i=0; i<8; i++)
|
|
{
|
|
if (instr->reg_cache_infos.needed_registers[i] != NULL)
|
|
{
|
|
code[j++] = 0x8B;
|
|
code[j++] = (i << 3) | 5;
|
|
*((unsigned int*)&code[j]) =
|
|
(unsigned int)instr->reg_cache_infos.needed_registers[i];
|
|
j+=4;
|
|
}
|
|
}
|
|
|
|
code[j++] = 0xC3;
|
|
}
|
|
|
|
void build_wrappers(precomp_instr *instr, int start, int end, precomp_block* block)
|
|
{
|
|
int i, reg;;
|
|
for (i=start; i<end; i++)
|
|
{
|
|
instr[i].reg_cache_infos.need_map = 0;
|
|
for (reg=0; reg<8; reg++)
|
|
{
|
|
if (instr[i].reg_cache_infos.needed_registers[reg] != NULL)
|
|
{
|
|
instr[i].reg_cache_infos.need_map = 1;
|
|
build_wrapper(&instr[i], instr[i].reg_cache_infos.jump_wrapper, block);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void simplify_access(void)
|
|
{
|
|
int i;
|
|
dst->local_addr = code_length;
|
|
for(i=0; i<8; i++) dst->reg_cache_infos.needed_registers[i] = NULL;
|
|
}
|
|
|