Commit graph

4 commits

Author SHA1 Message Date
Ilari Liusvaara
f49b82c989 Bus fixes: Reading of CPU MMIO registers does not update MDR
Also fixes controller timings to be more realistic.
2017-10-25 14:22:19 +03:00
Ilari Liusvaara
5544b9ba12 Don't try to enter loadstate with loadstate already in progress 2016-08-09 18:59:25 +03:00
Ilari Liusvaara
1834c61dfb Fix MSU-1 bug where write to MSU1BASE+4 is mirred to MSUBASE+5 2015-09-07 20:52:01 +03:00
Ilari Liusvaara
5ab3b133a4 Fix bsnes compilation for GCC 5.X 2015-08-08 11:13:39 +03:00