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50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/*
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Copyright (C) 2001,2005 StrmnNrmn
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#pragma once
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#ifndef SYSW32_DYNAREC_X64_DYNARECTARGETX64_H_
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#define SYSW32_DYNAREC_X64_DYNARECTARGETX64_H_
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// Intel register codes. Odd ordering is for intel bytecode
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enum EIntelReg {
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INVALID_CODE = 0xFFFFFFFF,
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RAX_CODE = 0,
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RCX_CODE = 1,
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RDX_CODE = 2,
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RBX_CODE = 3,
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RSP_CODE = 4,
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RBP_CODE = 5,
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RSI_CODE = 6,
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RDI_CODE = 7,
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R8_CODE = 8,
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R9_CODE = 9,
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R10_CODE = 10,
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R11_CODE = 11,
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R12_CODE = 12,
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R13_CODE = 13,
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R14_CODE = 14,
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R15_CODE = 15,
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NUM_X64_REGISTERS = 16,
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};
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#endif // SYSW32_DYNAREC_X64_DYNARECTARGETX64_H_
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