mirror of
https://github.com/DaedalusX64/daedalus.git
synced 2025-04-02 10:21:48 -04:00
327 lines
16 KiB
C++
327 lines
16 KiB
C++
/*
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Copyright (C) 2001,2005 StrmnNrmn
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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//Define to use jumptable dynarec
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//#define NEW_DYNAREC_COMPILER
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#pragma once
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#ifndef SYSPSP_DYNAREC_CODEGENERATORPSP_H_
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#define SYSPSP_DYNAREC_CODEGENERATORPSP_H_
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#include "DynaRec/CodeGenerator.h"
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#include "AssemblyWriterPSP.h"
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#include "DynarecTargetPSP.h"
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#include "DynaRec/N64RegisterCache.h"
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#include <stack>
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class CAssemblyBuffer;
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using CN64RegisterCachePSP = CN64RegisterCache<EPspReg>;
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class CCodeGeneratorPSP : public CCodeGenerator, public CAssemblyWriterPSP
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{
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public:
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CCodeGeneratorPSP( CAssemblyBuffer * p_buffer_a, CAssemblyBuffer * p_buffer_b );
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virtual void Initialise( u32 entry_address, u32 exit_address, u32 * hit_counter, const void * p_base, const SRegisterUsageInfo & register_usage );
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virtual void Finalise( ExceptionHandlerFn p_exception_handler_fn, const std::vector< CJumpLocation > & exception_handler_jumps, const std::vector< RegisterSnapshotHandle>& exception_handler_snapshots );
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virtual void UpdateRegisterCaching( u32 instruction_idx );
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virtual RegisterSnapshotHandle GetRegisterSnapshot();
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virtual CCodeLabel GetEntryPoint() const;
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virtual CCodeLabel GetCurrentLocation() const;
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virtual u32 GetCompiledCodeSize() const;
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virtual CJumpLocation GenerateExitCode( u32 exit_address, u32 jump_address, u32 num_instructions, CCodeLabel next_fragment );
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virtual void GenerateEretExitCode( u32 num_instructions, CIndirectExitMap * p_map );
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virtual void GenerateIndirectExitCode( u32 num_instructions, CIndirectExitMap * p_map );
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virtual void GenerateBranchHandler( CJumpLocation branch_handler_jump, RegisterSnapshotHandle snapshot );
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virtual CJumpLocation GenerateOpCode( const STraceEntry& ti, bool branch_delay_slot, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump);
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virtual CJumpLocation ExecuteNativeFunction( CCodeLabel speed_hack, bool check_return = false );
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private:
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// Not virtual base
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void SetVar( u32 * p_var, u32 value );
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void SetVar( u32 * p_var, EPspReg reg_src );
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void SetFloatVar( f32 * p_var, EPspFloatReg reg_src );
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void GetVar( EPspReg dst_reg, const u32 * p_var );
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void GetFloatVar( EPspFloatReg dst_reg, const f32 * p_var );
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void GetBaseRegisterAndOffset( const void * p_address, EPspReg * p_reg, s16 * p_offset );
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//void UpdateAddressAndDelay( u32 address, bool set_branch_delay );
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void GenerateCACHE( EN64Reg base, s16 offset, u32 cache_op );
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void GenerateJAL( u32 address );
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void GenerateJR( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateJALR( EN64Reg rs, EN64Reg rd, u32 address, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateMFLO( EN64Reg rd );
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void GenerateMFHI( EN64Reg rd );
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void GenerateMTLO( EN64Reg rs );
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void GenerateMTHI( EN64Reg rs );
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void GenerateMULT( EN64Reg rs, EN64Reg rt );
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void GenerateMULTU( EN64Reg rs, EN64Reg rt );
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void GenerateDIV( EN64Reg rs, EN64Reg rt );
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void GenerateDIVU( EN64Reg rs, EN64Reg rt );
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void GenerateADDU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSUBU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateAND( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateOR( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateXOR( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateNOR( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSLT( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSLTU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateDDIV( EN64Reg rs, EN64Reg rt );
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void GenerateDDIVU( EN64Reg rs, EN64Reg rt );
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void GenerateDMULTU( EN64Reg rs, EN64Reg rt );
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void GenerateDMULT( EN64Reg rs, EN64Reg rt );
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void GenerateDADDU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateDADDIU( EN64Reg rt, EN64Reg rs, s16 immediate );
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void GenerateDSRA32( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateDSRA( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateDSLL32( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateDSLL( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateADDIU( EN64Reg rt, EN64Reg rs, s16 immediate );
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void GenerateANDI( EN64Reg rt, EN64Reg rs, u16 immediate );
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void GenerateORI( EN64Reg rt, EN64Reg rs, u16 immediate );
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void GenerateXORI( EN64Reg rt, EN64Reg rs, u16 immediate );
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void GenerateLUI( EN64Reg rt, s16 immediate );
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void GenerateSLTI( EN64Reg rt, EN64Reg rs, s16 immediate );
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void GenerateSLTIU( EN64Reg rt, EN64Reg rs, s16 immediate );
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void GenerateSLL( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateSRL( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateSRA( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateLB ( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateLBU( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateLH ( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateLHU( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateLW ( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s16 offset );
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void GenerateLD ( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s16 offset );
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void GenerateLWC1( u32 current_pc, bool set_branch_delay, u32 ft, EN64Reg base, s32 offset );
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void GenerateLDC1( u32 current_pc, bool set_branch_delay, u32 ft, EN64Reg base, s32 offset );
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void GenerateLWL( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s16 offset );
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void GenerateLWR( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s16 offset );
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void GenerateSB( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateSH( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateSW( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateSD( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateSWC1( u32 current_pc, bool set_branch_delay, u32 ft, EN64Reg base, s32 offset );
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void GenerateSDC1( u32 current_pc, bool set_branch_delay, u32 ft, EN64Reg base, s32 offset );
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void GenerateSWL( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateSWR( u32 current_pc, bool set_branch_delay, EN64Reg rt, EN64Reg base, s32 offset );
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void GenerateMFC1( EN64Reg rt, u32 fs );
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void GenerateMTC1( u32 fs, EN64Reg rt );
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void GenerateCFC1( EN64Reg rt, u32 fs );
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void GenerateCTC1( u32 fs, EN64Reg rt );
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void GenerateADD_D_Sim( u32 fd, u32 fs, u32 ft );
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void GenerateSUB_D_Sim( u32 fd, u32 fs, u32 ft );
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void GenerateMUL_D_Sim( u32 fd, u32 fs, u32 ft );
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void GenerateDIV_D_Sim( u32 fd, u32 fs, u32 ft );
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void GenerateSQRT_D_Sim( u32 fd, u32 fs );
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void GenerateABS_D_Sim( u32 fd, u32 fs );
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void GenerateMOV_D_Sim( u32 fd, u32 fs );
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void GenerateNEG_D_Sim( u32 fd, u32 fs );
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void GenerateTRUNC_W_D_Sim( u32 fd, u32 fs );
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void GenerateCVT_W_D_Sim( u32 fd, u32 fs );
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void GenerateCVT_S_D_Sim( u32 fd, u32 fs );
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void GenerateCMP_D_Sim( u32 fs, ECop1OpFunction cmp_op, u32 ft );
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void GenerateADD_S( u32 fd, u32 fs, u32 ft );
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void GenerateSUB_S( u32 fd, u32 fs, u32 ft );
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void GenerateMUL_S( u32 fd, u32 fs, u32 ft );
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void GenerateDIV_S( u32 fd, u32 fs, u32 ft );
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void GenerateSQRT_S( u32 fd, u32 fs );
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void GenerateABS_S( u32 fd, u32 fs );
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void GenerateMOV_S( u32 fd, u32 fs );
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void GenerateNEG_S( u32 fd, u32 fs );
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void GenerateCMP_S( u32 fs, ECop1OpFunction cmp_op, u32 ft );
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void GenerateCVT_W_S( u32 fd, u32 fs );
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void GenerateCVT_D_S_Sim( u32 fd, u32 fs );
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void GenerateCVT_D_S( u32 fd, u32 fs );
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void GenerateCVT_D_W_Sim( u32 fd, u32 fs );
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void GenerateADD_D( u32 fd, u32 fs, u32 ft );
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void GenerateSUB_D( u32 fd, u32 fs, u32 ft );
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void GenerateMUL_D( u32 fd, u32 fs, u32 ft );
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void GenerateDIV_D( u32 fd, u32 fs, u32 ft );
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void GenerateSQRT_D( u32 fd, u32 fs );
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void GenerateMOV_D( u32 fd, u32 fs );
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void GenerateNEG_D( u32 fd, u32 fs );
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void GenerateCVT_S_W( u32 fd, u32 fs );
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void GenerateTRUNC_W_S( u32 fd, u32 fs );
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void GenerateFLOOR_W_S( u32 fd, u32 fs );
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void GenerateMFC0( EN64Reg rt, u32 fs );
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void GenerateMTC0( EN64Reg rt, u32 fs );
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CJumpLocation GenerateBranchAlways( CCodeLabel target );
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CJumpLocation GenerateBranchIfSet( const u32 * p_var, CCodeLabel target );
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CJumpLocation GenerateBranchIfNotSet( const u32 * p_var, CCodeLabel target );
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CJumpLocation GenerateBranchIfEqual( const u32 * p_var, u32 value, CCodeLabel target );
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CJumpLocation GenerateBranchIfNotEqual( const u32 * p_var, u32 value, CCodeLabel target );
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CJumpLocation GenerateBranchIfNotEqual( EPspReg reg_a, u32 value, CCodeLabel target );
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void GenerateBEQ( EN64Reg rs, EN64Reg rt, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBNE( EN64Reg rs, EN64Reg rt, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBLEZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBGTZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBLTZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBGEZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBC1F( const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBC1T( const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateSLLV( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSRLV( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSRAV( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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private:
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void SetRegisterSpanList( const SRegisterUsageInfo & register_usage, bool loops_to_self );
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void ExpireOldIntervals( u32 instruction_idx );
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void SpillAtInterval( const SRegisterSpan & live_span );
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EPspReg GetRegisterNoLoad( EN64Reg n64_reg, u32 lo_hi_idx, EPspReg scratch_reg );
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EPspReg GetRegisterNoLoadLo( EN64Reg n64_reg, EPspReg scratch_reg ) { return GetRegisterNoLoad( n64_reg, 0, scratch_reg ); }
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EPspReg GetRegisterNoLoadHi( EN64Reg n64_reg, EPspReg scratch_reg ) { return GetRegisterNoLoad( n64_reg, 1, scratch_reg ); }
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EPspReg GetRegisterAndLoad( EN64Reg n64_reg, u32 lo_hi_idx, EPspReg scratch_reg );
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EPspReg GetRegisterAndLoadLo( EN64Reg n64_reg, EPspReg scratch_reg ) { return GetRegisterAndLoad( n64_reg, 0, scratch_reg ); }
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EPspReg GetRegisterAndLoadHi( EN64Reg n64_reg, EPspReg scratch_reg ) { return GetRegisterAndLoad( n64_reg, 1, scratch_reg ); }
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void GetRegisterValue( EPspReg psp_reg, EN64Reg n64_reg, u32 lo_hi_idx );
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void LoadRegister( EPspReg psp_reg, EN64Reg n64_reg, u32 lo_hi_idx );
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void LoadRegisterLo( EPspReg psp_reg, EN64Reg n64_reg ) { LoadRegister( psp_reg, n64_reg, 0 ); }
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void LoadRegisterHi( EPspReg psp_reg, EN64Reg n64_reg ) { LoadRegister( psp_reg, n64_reg, 1 ); }
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void PrepareCachedRegister( EN64Reg n64_reg, u32 lo_hi_idx );
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void PrepareCachedRegisterLo( EN64Reg n64_reg ) { PrepareCachedRegister( n64_reg, 0 ); }
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void PrepareCachedRegisterHi( EN64Reg n64_reg ) { PrepareCachedRegister( n64_reg, 1 ); }
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void StoreRegister( EN64Reg n64_reg, u32 lo_hi_idx, EPspReg psp_reg );
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void StoreRegisterLo( EN64Reg n64_reg, EPspReg psp_reg ) { StoreRegister( n64_reg, 0, psp_reg ); }
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void StoreRegisterHi( EN64Reg n64_reg, EPspReg psp_reg ) { StoreRegister( n64_reg, 1, psp_reg ); }
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void SetRegister64( EN64Reg n64_reg, s32 lo_value, s32 hi_value );
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void SetRegister32s( EN64Reg n64_reg, s32 value );
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void SetRegister( EN64Reg n64_reg, u32 lo_hi_idx, u32 value );
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/*
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enum EUpdateRegOptions
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{
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URO_HI_SIGN_EXTEND, // Sign extend from src
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URO_HI_CLEAR, // Clear hi bits
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};
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*/
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void UpdateRegister( EN64Reg n64_reg, EPspReg psp_reg, bool options );
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EPspFloatReg GetFloatRegisterAndLoad( EN64FloatReg n64_reg );
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void UpdateFloatRegister( EN64FloatReg n64_reg );
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EPspFloatReg GetSimFloatRegisterAndLoad( EN64FloatReg n64_reg );
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void UpdateSimDoubleRegister( EN64FloatReg n64_reg );
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const CN64RegisterCachePSP & GetRegisterCacheFromHandle( RegisterSnapshotHandle snapshot ) const;
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void FlushRegister( CN64RegisterCachePSP & cache, EN64Reg n64_reg, u32 lo_hi_idx, bool invalidate );
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void FlushAllRegisters( CN64RegisterCachePSP & cache, bool invalidate );
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void FlushAllFloatingPointRegisters( CN64RegisterCachePSP & cache, bool invalidate );
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void FlushAllTemporaryRegisters( CN64RegisterCachePSP & cache, bool invalidate );
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void RestoreAllRegisters( CN64RegisterCachePSP & current_cache, CN64RegisterCachePSP & new_cache );
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void GenerateGenericR4300( OpCode op_code, CPU_Instruction p_instruction );
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using ReadMemoryFunction = u32 (*)(u32 address, u32 current_pc );
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using WriteMemoryFunction = void (*)( u32 address, u32 value, u32 current_pc );
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bool GenerateDirectLoad( EPspReg psp_dst, EN64Reg n64_base, s16 offset, OpCodeValue load_op, u32 swizzle );
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void GenerateSlowLoad( u32 current_pc, EPspReg psp_dst, EPspReg reg_address, ReadMemoryFunction p_read_memory );
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void GenerateLoad( u32 current_pc, EPspReg psp_dst, EN64Reg n64_base, s16 offset, OpCodeValue load_op, u32 swizzle, ReadMemoryFunction p_read_memory );
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bool GenerateDirectStore( EPspReg psp_src, EN64Reg n64_base, s16 offset, OpCodeValue store_op, u32 swizzle );
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void GenerateStore( u32 current_pc,
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EPspReg psp_src,
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EN64Reg base,
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s32 offset,
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OpCodeValue store_op,
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u32 swizzle,
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WriteMemoryFunction p_write_memory );
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void GenerateSlowStore( u32 current_pc, EPspReg psp_src, EPspReg reg_address, WriteMemoryFunction p_write_memory );
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struct SAddressCheckFixup
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{
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CJumpLocation BranchToJump; // Branches to our jump loc
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CCodeLabel HandlerAddress; // Address of our handler function in the second buffer
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SAddressCheckFixup( CJumpLocation branch, CCodeLabel label ) : BranchToJump( branch ), HandlerAddress( label ) {}
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};
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void GenerateAddressCheckFixups();
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void GenerateAddressCheckFixup( const SAddressCheckFixup & fixup );
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private:
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const u8 * mpBasePointer;
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EPspReg mBaseRegister;
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RegisterSpanList mRegisterSpanList;
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u32 mEntryAddress;
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CCodeLabel mLoopTop;
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bool mUseFixedRegisterAllocation;
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std::vector< CN64RegisterCachePSP > mRegisterSnapshots;
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CN64RegisterCachePSP mRegisterCache;
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// For register allocation
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RegisterSpanList mActiveIntervals;
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std::stack<EPspReg> mAvailableRegisters;
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bool mQuickLoad;
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EN64Reg mPreviousLoadBase;
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EN64Reg mPreviousStoreBase;
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bool mFloatCMPIsValid;
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bool mMultIsValid;
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std::vector< SAddressCheckFixup > mAddressCheckFixups;
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};
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#endif // SYSPSP_DYNAREC_CODEGENERATORPSP_H_
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