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https://github.com/DaedalusX64/daedalus.git
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63 lines
No EOL
1.9 KiB
C
63 lines
No EOL
1.9 KiB
C
/*
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Copyright (C) 2020 MasterFeizz
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#pragma once
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#include "Core/R4300OpCode.h"
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// ARM register codes.
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enum EArmReg
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{
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ArmReg_R0 = 0, ArmReg_R1, ArmReg_R2, ArmReg_R3,
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ArmReg_R4, ArmReg_R5, ArmReg_R6, ArmReg_R7,
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ArmReg_R8, ArmReg_R9, ArmReg_R10, ArmReg_R11,
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ArmReg_R12, ArmReg_R13, ArmReg_R14, ArmReg_R15,
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NUM_ARM_REGISTERS = 16,
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//Aliases
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};
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enum EArmVfpReg
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{
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ArmVfpReg_S0 = 0, ArmVfpReg_S1, ArmVfpReg_S2, ArmVfpReg_S3,
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ArmVfpReg_S4, ArmVfpReg_S5, ArmVfpReg_S6, ArmVfpReg_S7,
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ArmVfpReg_S8, ArmVfpReg_S9, ArmVfpReg_S10, ArmVfpReg_S11,
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ArmVfpReg_S12, ArmVfpReg_S13, ArmVfpReg_S14, ArmVfpReg_S15,
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ArmVfpReg_S16, ArmVfpReg_S17, ArmVfpReg_S18, ArmVfpReg_S19,
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ArmVfpReg_S20, ArmVfpReg_S21, ArmVfpReg_S22, ArmVfpReg_S23,
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ArmVfpReg_S24, ArmVfpReg_S25, ArmVfpReg_S26, ArmVfpReg_S27,
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ArmVfpReg_S28, ArmVfpReg_S29, ArmVfpReg_S30, ArmVfpReg_S31,
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NUM_VFP_REGISTERS = 32,
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//Aliases
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};
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// ARM conditions. Do NOT reorder these
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enum EArmCond
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{
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EQ, NE, CS, CC, MI, PL, VS, VC,
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HI, LS, GE, LT, GT, LE, AL, NV
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};
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// Return true if this register dont need sign extension //Corn
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inline bool N64Reg_DontNeedSign( EN64Reg n64_reg ) { return (0x30000001 >> n64_reg) & 1;}
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inline bool Reg_IsTemporary(EArmReg reg) { return false; } |