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https://github.com/DaedalusX64/daedalus.git
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214 lines
6.6 KiB
ArmAsm
214 lines
6.6 KiB
ArmAsm
#include "as_reg_compat.h"
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.set noreorder
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.set noat
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#define BadVAddr $8 // Address for the most recent address-related exception
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#define Status $12 // Processor status and control
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#define Cause $13 // Cause of last general exception
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#define EPC $14 // Program counter at last exception
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#define PRId $15 // Processor identification and revision
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#define FSR $31
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#define FIR $0
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#define REG_GPR_0 (6*4)
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#define REG_GPR_1 (REG_GPR_0 + 4)
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#define REG_GPR_2 (REG_GPR_1 + 4)
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#define REG_GPR_3 (REG_GPR_2 + 4)
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#define REG_GPR_4 (REG_GPR_3 + 4)
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#define REG_GPR_5 (REG_GPR_4 + 4)
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#define REG_GPR_6 (REG_GPR_5 + 4)
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#define REG_GPR_7 (REG_GPR_6 + 4)
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#define REG_GPR_8 (REG_GPR_7 + 4)
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#define REG_GPR_9 (REG_GPR_8 + 4)
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#define REG_GPR_10 (REG_GPR_9 + 4)
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#define REG_GPR_11 (REG_GPR_10 + 4)
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#define REG_GPR_12 (REG_GPR_11 + 4)
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#define REG_GPR_13 (REG_GPR_12 + 4)
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#define REG_GPR_14 (REG_GPR_13 + 4)
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#define REG_GPR_15 (REG_GPR_14 + 4)
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#define REG_GPR_16 (REG_GPR_15 + 4)
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#define REG_GPR_17 (REG_GPR_16 + 4)
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#define REG_GPR_18 (REG_GPR_17 + 4)
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#define REG_GPR_19 (REG_GPR_18 + 4)
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#define REG_GPR_20 (REG_GPR_19 + 4)
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#define REG_GPR_21 (REG_GPR_20 + 4)
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#define REG_GPR_22 (REG_GPR_21 + 4)
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#define REG_GPR_23 (REG_GPR_22 + 4)
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#define REG_GPR_24 (REG_GPR_23 + 4)
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#define REG_GPR_25 (REG_GPR_24 + 4)
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#define REG_GPR_26 (REG_GPR_25 + 4)
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#define REG_GPR_27 (REG_GPR_26 + 4)
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#define REG_GPR_28 (REG_GPR_27 + 4)
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#define REG_GPR_29 (REG_GPR_28 + 4)
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#define REG_GPR_30 (REG_GPR_29 + 4)
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#define REG_GPR_31 (REG_GPR_30 + 4)
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#define REG_STATUS (REG_GPR_31 + 4)
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#define REG_LO (REG_STATUS + 4)
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#define REG_HI (REG_LO + 4)
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#define REG_BADVADDR (REG_HI + 4)
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#define REG_CAUSE (REG_BADVADDR + 4)
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#define REG_EPC (REG_CAUSE + 4)
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#define REG_FPR_0 (REG_EPC + 4)
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#define REG_FPR_1 (REG_FPR_0 + 4)
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#define REG_FPR_2 (REG_FPR_1 + 4)
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#define REG_FPR_3 (REG_FPR_2 + 4)
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#define REG_FPR_4 (REG_FPR_3 + 4)
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#define REG_FPR_5 (REG_FPR_4 + 4)
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#define REG_FPR_6 (REG_FPR_5 + 4)
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#define REG_FPR_7 (REG_FPR_6 + 4)
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#define REG_FPR_8 (REG_FPR_7 + 4)
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#define REG_FPR_9 (REG_FPR_8 + 4)
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#define REG_FPR_10 (REG_FPR_9 + 4)
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#define REG_FPR_11 (REG_FPR_10 + 4)
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#define REG_FPR_12 (REG_FPR_11 + 4)
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#define REG_FPR_13 (REG_FPR_12 + 4)
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#define REG_FPR_14 (REG_FPR_13 + 4)
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#define REG_FPR_15 (REG_FPR_14 + 4)
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#define REG_FPR_16 (REG_FPR_15 + 4)
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#define REG_FPR_17 (REG_FPR_16 + 4)
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#define REG_FPR_18 (REG_FPR_17 + 4)
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#define REG_FPR_19 (REG_FPR_18 + 4)
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#define REG_FPR_20 (REG_FPR_19 + 4)
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#define REG_FPR_21 (REG_FPR_20 + 4)
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#define REG_FPR_22 (REG_FPR_21 + 4)
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#define REG_FPR_23 (REG_FPR_22 + 4)
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#define REG_FPR_24 (REG_FPR_23 + 4)
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#define REG_FPR_25 (REG_FPR_24 + 4)
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#define REG_FPR_26 (REG_FPR_25 + 4)
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#define REG_FPR_27 (REG_FPR_26 + 4)
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#define REG_FPR_28 (REG_FPR_27 + 4)
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#define REG_FPR_29 (REG_FPR_28 + 4)
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#define REG_FPR_30 (REG_FPR_29 + 4)
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#define REG_FPR_31 (REG_FPR_30 + 4)
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#define REG_FSR (REG_FPR_31 + 4)
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#define REG_FIR (REG_FSR + 4)
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#define REG_FP (REG_FIR + 4)
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.extern exception_regs
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.extern curr_handler
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.global _pspDebugExceptionHandler
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.ent _pspDebugExceptionHandler
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_pspDebugExceptionHandler:
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nop
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nop
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lw $v0, exception_regs
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sw $0, REG_GPR_0($v0)
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sw $1, REG_GPR_1($v0)
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cfc0 $1, $4 # Get original v0
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sw $1, REG_GPR_2($v0)
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cfc0 $1, $5 # Get original v1
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sw $1, REG_GPR_3($v0)
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sw $4, REG_GPR_4($v0)
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sw $5, REG_GPR_5($v0)
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sw $6, REG_GPR_6($v0)
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sw $7, REG_GPR_7($v0)
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sw $8, REG_GPR_8($v0)
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sw $9, REG_GPR_9($v0)
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sw $10, REG_GPR_10($v0)
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sw $11, REG_GPR_11($v0)
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sw $12, REG_GPR_12($v0)
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sw $13, REG_GPR_13($v0)
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sw $14, REG_GPR_14($v0)
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sw $15, REG_GPR_15($v0)
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sw $16, REG_GPR_16($v0)
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sw $17, REG_GPR_17($v0)
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sw $18, REG_GPR_18($v0)
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sw $19, REG_GPR_19($v0)
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sw $20, REG_GPR_20($v0)
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sw $21, REG_GPR_21($v0)
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sw $22, REG_GPR_22($v0)
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sw $23, REG_GPR_23($v0)
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sw $24, REG_GPR_24($v0)
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sw $25, REG_GPR_25($v0)
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sw $26, REG_GPR_26($v0)
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sw $27, REG_GPR_27($v0)
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sw $28, REG_GPR_28($v0)
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sw $29, REG_GPR_29($v0)
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sw $30, REG_GPR_30($v0)
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sw $31, REG_GPR_31($v0)
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mflo $v1
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sw $v1, REG_LO($v0)
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mfhi $v1
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sw $v1, REG_HI($v0)
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mfc0 $v1, BadVAddr
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sw $v1, REG_BADVADDR($v0)
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mfc0 $v1, Cause
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sw $v1, REG_CAUSE($v0)
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mfc0 $v1, EPC
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sw $v1, REG_EPC($v0)
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mfc0 $v1, Status
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sw $v1, REG_STATUS($v0)
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# Check if cop1 is enable and skip if not
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lui $a0, 0x2000
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and $a0, $a0, $v1
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beq $a0, $0, 1f
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nop
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swc1 $0, REG_FPR_0($v0)
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swc1 $1, REG_FPR_1($v0)
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swc1 $2, REG_FPR_2($v0)
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swc1 $3, REG_FPR_3($v0)
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swc1 $4, REG_FPR_4($v0)
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swc1 $5, REG_FPR_5($v0)
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swc1 $6, REG_FPR_6($v0)
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swc1 $7, REG_FPR_7($v0)
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swc1 $8, REG_FPR_8($v0)
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swc1 $9, REG_FPR_9($v0)
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swc1 $10, REG_FPR_10($v0)
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swc1 $11, REG_FPR_11($v0)
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swc1 $12, REG_FPR_12($v0)
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swc1 $13, REG_FPR_13($v0)
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swc1 $14, REG_FPR_14($v0)
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swc1 $15, REG_FPR_15($v0)
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swc1 $16, REG_FPR_16($v0)
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swc1 $17, REG_FPR_17($v0)
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swc1 $18, REG_FPR_18($v0)
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swc1 $19, REG_FPR_19($v0)
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swc1 $20, REG_FPR_20($v0)
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swc1 $21, REG_FPR_21($v0)
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swc1 $22, REG_FPR_22($v0)
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swc1 $23, REG_FPR_23($v0)
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swc1 $24, REG_FPR_24($v0)
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swc1 $25, REG_FPR_25($v0)
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swc1 $26, REG_FPR_26($v0)
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swc1 $27, REG_FPR_27($v0)
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swc1 $28, REG_FPR_28($v0)
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swc1 $29, REG_FPR_29($v0)
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swc1 $30, REG_FPR_30($v0)
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swc1 $31, REG_FPR_31($v0)
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cfc1 $t0, FSR
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sw $t0, REG_FSR($v0)
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cfc1 $t0, FIR
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sw $t0, REG_FIR($v0)
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ctc1 $0, FSR # Clear any cause flags
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# Jump target for ignore cop1
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1:
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sw $sp, REG_FP($v0)
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move $a0, $v0
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lw $2, curr_handler
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mtc0 $2, $14
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nop
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nop
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eret
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nop
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nop
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.end _pspDebugExceptionHandler
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#include "pspimport.s"
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IMPORT_START "ExceptionManagerForKernel",0x00010011
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IMPORT_FUNC "ExceptionManagerForKernel",0x565C0B0E,sceKernelRegisterDefaultExceptionHandler371
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